CY62138EV30
MoBL®
Document #: 38-05577 Rev. *A
Page 5 of 9
Switching Characteristics (Over the Operating Range)[9]
Parameter
Description
45 ns
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
45
ns
tAA
Address to Data Valid
45
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE LOW to Data Valid
45
ns
tDOE
OE LOW to Data Valid
22
ns
tLZOE
OE LOW to Low Z[10]
5ns
tHZOE
OE HIGH to High Z[10,11]
18
ns
tLZCE
CE LOW to Low Z[10]
10
ns
tHZCE
CE HIGH to High Z[10, 11]
18
ns
tPU
CE LOW to Power-up
0
ns
tPD
CE HIGH to Power-up
45
ns
Write Cycle[12]
tWC
Write Cycle Time
45
ns
tSCE
CE LOW to Write End
35
ns
tAW
Address Set-up to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tSD
Data Set-up to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z[10, 11]
18
ns
tLZWE
WE HIGH to Low Z[10]
10
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
Notes:
9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2,
input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” section.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high-impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
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