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CY22800
Document #: 001-07704 Rev. *A
Page 8 of 10
Test Circuit
Figure 2. Test Circuit Diagram
Timing Definitions
Figure 3. Duty Cycle Definition; DC = t2/t1
Figure 4. Rise and Fall Time Definitions
DC Electrical Specifications
Parameter
Name
Description
Min.
Typ.
Max. Unit
IOH
Output High Current
VOH = VDD – 0.5, VDD = 3.3V (source)
12
24
–
mA
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V (sink)
12
24
–
mA
CIN1
Input Capacitance
All input pins except XIN and XOUT
–
–
7
pF
CIN2
Input Capacitance
XIN and XOUT pins for non-VCXO applica-
tions
–24
–
pF
IIH
Input High Current
VIH = VDD
–5
10
µA
IIL
Input Low Current
VIL = 0V
–
–
50
µA
f∆XO
VCXO Pullability Range
±150
–
ppm
VVCXO
VCXO Input Range
0
–
VDD
V
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
–
–
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
––
0.3
VDD
AC Electrical Characteristics (VDD = 3.3V)
Parameter
Name
Description
Min.
Typ.
Max. Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 3, 50% of VDD
45
50
55
%
t3
Rising Edge Slew Rate
Output Clock Rise Time, 20% - 80% of VDD
0.8
1.4
–
V/ns
t4
Falling Edge Slew Rate
Output Clock Fall Time, 80% - 20% of VDD
0.8
1.4
–
V/ns
t10
PLL Lock Time
–
–
3
ms
0.1
µF
VDD
CLKout
CLOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
t3
CLK
80%
20%
t4
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