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LA6548ND Datasheet(PDF) 5 Page - Sanyo Semicon Device |
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LA6548ND Datasheet(HTML) 5 Page - Sanyo Semicon Device |
5 / 7 page LA6548ND No.8767-5/7 Continued from preceding page. Pin No. Pin Description Equivalent circuit 5 6 11 10 20 21 26 25 VO1+ VO1- VO2+ VO2- VO3+ VO3- VO4+ VO4- Output pins. 2 MUTE Muting control input. The outputs will be on when the MUTE pin is at the high level. The outputs will be off when the MUTE pin is at the low level ; in particular, the outputs go to the high-impedance state at this time. 29 VREF Reference voltage input. 16 RESET Reset output. When REG C (3.3VREG) is high, RESET will be high. When REG C (3.3VREG) is low, RESET will be low. Details of Operating voltage see section Reset operation. 17 CD Reset output delay time setting. The delay time until the point the reset output switches from low to high is set by the capacitor connected between this pin and ground. Reference to Reset operation. 33k Ω VCC VCC GND GND VO*-/+ 40k Ω 30k Ω VCC VCC GND MUTE VCC VCC GND GND VREF RESET GND VCC REG_C (3.3VREG) GND VCC CD GND GND |
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