CY62126DV30 MoBL®
Document #: 38-05230 Rev. *H
Page 5 of 12
Switching Characteristics (Over the Operating Range)[10]
Parameter
Description
CY62126DV30-55
Unit
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
ns
tAA
Address to Data Valid
55
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE LOW to Data Valid
55
ns
tDOE
OE LOW to Data Valid
25
ns
tLZOE
OE LOW to Low Z[11]
5
ns
tHZOE
OE HIGH to High Z[11, 12]
20
ns
tLZCE
CE LOW to Low Z[11]
10
ns
tHZCE
CE HIGH to High Z[11, 12]
20
ns
tPU
CE LOW to Power-up
0
ns
tPD
CE HIGH to Power-down
55
ns
tDBE
BLE/BHE LOW to Data Valid
25
ns
tLZBE
BLE/BHE LOW to Low Z[11]
5
ns
tHZBE
BLE/BHE HIGH to High-Z[11, 12]
20
ns
Write Cycle[13]
tWC
Write Cycle Time
55
ns
tSCE
CE LOW to Write End
40
ns
tAW
Address Set-up to Write End
40
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
40
ns
tBW
BLE/BHE LOW to Write End
40
ns
tSD
Data Set-up to Write End
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High Z[11, 12]
20
ns
tLZWE
WE HIGH to Low Z[11]
10
ns
Notes:
10. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of
the specified IOL.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
13. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
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