CY29940AXI datasheet(3/7 Pages) CYPRESS

Part #	CY29940AXI

Description	2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY29940

Document #: 38-07283 Rev. *C

Page 3 of 7

Notes:

8.

Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.

9.

Across temperature and voltage ranges, includes output skew.

10. For a specific temperature and voltage, includes output skew

11. Parameters tested @ 150 MHz.

AC Parameters[8]: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%, TA = –40°C to +85°C

Parameter

Description

Conditions

Min.

Typ.

Max.

Unit.

Fmax

Input Frequency

–

200

MHz

tPD

PECL_CLK to Q Delay[5, 6, 11]

</=150 MHz

VDD = 3.3V

85°C

tPHL

2.0

–

3.2

ns

tPLH

2.1

–

3.4

VDD = 3.3V

70°C

tPHL

1.9

–

3.1

tPLH

2.0

–

3.2

VDD = 2.5V

85°C

tPHL

2.5

–

5.2

tPLH

2.6

–

5

VDD = 2.5V

70°C

tPHL

2.5

–

5

tPLH

2.6

–

5

tPD

LVCMOS to Q Delay[5, 6, 11]

</=150 MHz

VDD = 3.3V

85°C

tPHL

1.9

–

3

ns

tPLH

2.0

–

3.2

VDD = 3.3V

70°C

tPHL

1.8

–

2.9

tPLH

1.8

–

3.1

VDD = 2.5V

85°C

tPHL

2.5

–

4

tPLH

2.5

–

4

VDD = 2.5V

70°C

tPHL

2.3

–

3.8

tPLH

2.3

–

3.8

tJ

Total Jitter

VDD = 3.3V @ 150MHz

–

10

ps

FoutDC

Output Duty Cycle[5, 6, 7]

FCLK < 134 MHz

–

55

%

FCLK > 134 MHz

–

60

Tskew

Output-to-Output Skew[5, 6]

VDD = 3.3V

–

60

150

ps

VDD = 2.5V

–

200

Tskew(pp)

Part-to-Part Skew[9]

PECL, VDDC = 3.3V

–

1.4

ns

PECL, VDDC = 2.5V

–

2.2

Tskew(pp)

Part-to-Part Skew[9]

TCLK, VDDC = 3.3V

–

1.2

ns

TCLK, VDDC = 2.5V

–

1.7

Tskew(pp)

Part to Part Skew[10]

PECL_CLK

–

850

ps

TCLK

–

750

tR/tF

Output Clocks Rise/Fall Time[5, 6] 0.7V to 2.0V,

VDDC = 3.3V

0.3

–

1.1

ns

0.5V to 1.8V,

VDDC = 2.5V

0.3

–

1.2

[+] Feedback

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