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CY25701JXC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY25701JXC
Description  Programmable High-Frequency Crystal Oscillator with Spread Spectrum (SSXO) and No-Spread Spectrum (XO) Option
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY25701JXC Datasheet(HTML) 3 Page - Cypress Semiconductor

   
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CY25701JXC/FJXC
Document #: 38-07684 Rev. *E
Page 3 of 7
Absolute Maximum Rating
Supply Voltage (VDD) .................................... –0.5V to +7.0V
DC Input Voltage ....................................–0.5V to VDD + 0.5V
Storage Temperature (Non-condensing) .... –55°C to +100°C
Junction Temperature ................................ –40°C to +125°C
Data Retention @ Tj = 125
°C................................> 10 years
Package Power Dissipation...................................... 350 mW
Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Unit
VDD
Supply Voltage
3.00
3.30
3.60
V
TA
Ambient Temperature
–20
70
°C
CLOAD
Max. Load Capacitance @ pin 3
15
pF
FSSCLK
SSCLK output frequency, CLOAD = 15 pF
10
166
MHz
FMOD
Spread Spectrum Modulation Frequency
30.0
31.5
33.0
kHz
TPU
Power-up time for VDD to reach minimum specified voltage (power ramp must
be monotonic)
0.05
500
ms
DC Electrical Characteristics
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
IOH
Output High Current (pin 3)
VOH = VDD – 0.5, VDD = 3.3V (source)
10
12
mA
IOL
Output Low Current (pin 3)
VOL = 0.5, VDD= 3.3V (sink)
10
12
mA
VIH
Input High Voltage (pin 1)
CMOS levels, 70% of VDD
0.7VDD
–VDD
V
VIL
Input Low Voltage (pin 1)
CMOS levels, 30% of VDD
VSS
–0.3VDD
V
IIH
Input High Current (pin 1)
Vin = VDD
––
10
µA
IIL
Input Low Current (pin 1)
Vin = VSS
––
10
µA
IOZ
Output Leakage Current (pin 3) Three-state output, OE = 0
–10
10
µA
CIN
[2]
Input Capacitance (pin 1)
Pin 1, or OE
5
7
pF
IVDD
Supply Current
VDD = 3.3V, SSCLK = 10 to 166 MHz, CLOAD
= 0, OE = VDD
––
50
mA
∆fAging
TA = 25°C, First year
–5
5
ppm
AC Electrical Characteristics[2]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
SSCLK, Measured at VDD/2
45
50
55
%
tR
Output Rise Time
20%–80% of VDD, CL = 15 pF
2.7
ns
tF
Output Fall Time
20%–80% of VDD, CL = 15 pF
2.7
ns
TCCJ1
[3]
Cycle-to-Cycle Jitter SSCLK
(Pin 3)
SSCLK
≥133 MHz, Measured at V
DD/2
85
200
ps
25 MHz
≤ SSCLK <133 MHz, Measured at
VDD/2
215
400
ps
SSCLK < 25 MHz, Measured at VDD/2
1% of
1/SSCK
s
TOE1
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped
outputs (Asynchronous)
150
350
ns
TOE2
Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
150
350
ns
TLOCK
PLL Lock Time
Time for SSCLK to reach valid frequency
10
ms
Notes:
2. Guaranteed by characterization, not 100% tested.
3. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer
to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your
local Cypress Field Application Engineer.
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