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CY25403 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY25403
Description  Three PLL Programmable Clock Generator with Spread Spectrum
Download  8 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY25403 Datasheet(HTML) 3 Page - Cypress Semiconductor

   
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PRELIMINARY
CY25403
CY25423
Document #: 001-12564 Rev. *A
Page 3 of 8
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
Supply Voltage
–0.5
4.5
V
VIN
Input Voltage
Relative to VSS
–0.5
VDD + 0.5 VDC
TS
Temperature, Storage
Non Functional
–65
+150
°C
ESDHBM
ESD Protection (Human
Body Model)
MIL-STD-883, Method 3015
2000
Volts
UL-94
Flammability Rating
@1/8 in.
V-0
MSL
Moisture Sensitivity Level
SOIC package
1
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max. Unit
VDD1
Operating Voltage, 3.3V
3.0
3.6
V
VDD2
Operating Voltage, 3.0V
2.7
3.3
V
VDD3
Operating Voltage, 2.5V
2.25
2.75
V
VDD4
Operating Voltage, 1.8V
1.65
1.95
V
TAC
Commercial Ambient Temperature
0
+70
°C
TAI
Industrial Ambient Temperature
–40
+85
°C
CLOAD
Max. Load Capacitance
15
pF
tPU
Power-up time for all VDD pins to reach minimum specified voltage (power ramps must
be monotonic)
0.05
500
ms
DC Electrical Specifications
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VOL
Output Low Voltage, All CLK pins
All VDD levels, IOL = 8 mA
0
0.4
V
VOH
Output High Voltage, All CLK pins
All VDD levels, IOH = –8 mA
VDD – 0.4
VDD
V
VIL
All Inputs except XIN
All VDD levels
–0.3
0.2 * VDD
V
VIH
All Inputs except XIN
All VDD levels
0.8 * VDD
–VDD + 0.3
V
VILX
Input Low Voltage, clock input to XIN pin
All VDD levels
–0.3
0.36
V
VIHX
Input High Voltage, clock input to XIN pin
All VDD levels
1.44
2.0
V
IILPDOE
Input Low Current, PD#/OE and FS0,1 pins VIN = VSS
(Internal pull up = 100k typical)
––
10
μA
IIHPDOE
Input High Current, PD#/OE and FS0,1 pins VIN = VDD
(Internal pull up = 100k typical)
––
1
μA
IILSR
Input Low Current, SSON pin
VIN = VSS
(Internal pull down = 100k typical)
––
1
μA
IIHSR
Input High Current, SSON pin
VIN = VDD
(Internal pull down = 100k typical)
––
10
μA
IDD
[1]
Supply Current
All clocks running, CL = 0
––
17
mA
CIN
Input Capacitance - All inputs except XIN
SSON, OE, PD# or FS inputs
––
7
pF
Note
1. Configuration dependent.
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