CY24488 datasheet(4/15 Pages) CYPRESS

Part #	CY24488

Description	Quad PLL Clock Generator with Serial Interface (I2C)

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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4 / 15 page

CY24488

Document #: 001-09608 Rev. *A

Page 4 of 15

Programming Flow

The device registers may be programmed in any sequence,

but for convenience, a suggested programming flow is shown

in Figure 2.

Any step in this programming sequence may be skipped if the

default value is the desired value.

When programming an output frequency, the new frequency

will be valid on that output after all of the specified data values

have been written to all of the specified addresses. When

changing an output frequency, the output may transition

through one or more indeterminate frequencies between the

writing of the first byte and the last byte.

Note that some of the programming steps are not as

independent as they appear in the flow diagram. In particular,

addresses 48H, 53H, and 57H control both output frequencies

and drive strength. Because a byte is the smallest unit that

may be programmed through the serial interface, the user

must consider both the frequency setting and the output drive

strength when constructing the byte value to be written into

these particular address. It is not necessary to write more than

once to any given address, but that one write must have all of

the bits set correctly.

Example: configure CLKC for 33.8688 MHz and 2.5V output.

For address 48H, start with the value in Table 4: 89H (binary

10001001). Table 9 shows that bits 7 & 6 control the drive

st

r

engt

h,whi

chshoul

dbe‘

11’(

f

r

omTable 10). Therefore, the

final value is 11001001, which is C9H. This value is written

once.

Figure 2. Programming Flow

Default

Output Supply

Voltage settings if

2.5V (Table 3)

Drive Strength

settings for 2.5V

or EMI

(Tables 9, 4, 6, 8)

Reference CLK &

Crystal settings

(Table 2)

CLKC, D & E

Frequency settings

(Tables 4 - 6)

CLKF & G

Frequency settings

(Tables 7 - 8)

Table 2. Register Settings for VCXO and Reference

Reference Clock and VCXO

Crystal

Address

Manufacturer Part No.

Package

Specified CL

16H

17H

CLKIN (external reference), VCXO off

–

89

3A

Crystal, VCXO off

any

10.7 pF

88

4F

Crystal, VCXO off

any

12 pF

88

5F

Crystal, VCXO off (default)

any

12.6 pF

88

67

Crystal, VCXO off

any

14 pF

88

77

Crystal, VCXO on

KDS DSX530GA

5x3.2 mm

12.6 pF

88

3A

Crystal, VCXO on

KDS DSX530GA

5x3.2 mm

10.7 pF

88

2A

Crystal, VCXO on

RIVER FCX-03

5x3.2 mm

12 pF

88

41

Crystal, VCXO on

KDK

5x3.2 mm

12 pF

88

3A

Crystal, VCXO on

KDS

SMD-49

12 pF

88

39

Crystal, VCXO on

Ecliptek ECX-6277

SMD-49

12 pF

88

41

Table 3. Register Settings for Output Supply Voltages

Output

Output Supply Voltages

Address

41H

43H

CLKC

VDD1 = 3.3V

BF (default)

–

VDD1 = 2.5V

7F

–

CLKD, CLKE, CLKF, CLKG

VDD2 = 3.3V

–

A0 (default)

VDD2 = 2.5V

–

90

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