CY14B104L/CY14B104N
PRELIMINARY
Document #: 001-07102 Rev. *E
Page 5 of 21
Upon
completion
of
the
STORE
operation
the
CY14B104L/CY14B104N remains disabled until the HSB pin
returns high. Leave the HSB unconnected if is not used.
Hardware RECALL (Power Up)
During power
up or
after any
low
power condition
(VCC< VSWITCH), an internal RECALL request will be latched.
When VCC once again exceeds the sense voltage of VSWITCH,
a RECALL cycle will automatically be initiated and takes
tHRECALL to complete.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with
a software address sequence. The CY14B104L/CY14B104N
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence. If there are
intervening READ or WRITE accesses, the sequence will be
aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled
READs or OE controlled READs. Once the sixth address in the
sequence has been entered, the STORE cycle commences
and the chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence, although it is
not necessary that OE be low for the sequence to be valid.
After the tSTORE cycle time has been fulfilled, the SRAM will
again be activated for READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner
similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE controlled READ
operations must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared and second, the nonvolatile information is
transferred into the SRAM cells. After the tRECALL cycle time
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation does not alter the data in
the nonvolatile elements.
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