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CY22388 Datasheet(PDF) 2 Page - Cypress Semiconductor

Part No. CY22388
Description  Factory Programmable Quad PLL Clock Generator with VCXO
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY22388 Datasheet(HTML) 2 Page - Cypress Semiconductor

 
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CY22388/89/91
Document #: 38-07734 Rev. *B
Page 2 of 10
General Description
The CY22388 family of devices has an Analog VCXO (Voltage
Controlled Crystal Oscillator), 4 PLLs, up to 8 clock outputs
and frequency selection capabilities. The frequency selects do
not modify any PLL frequency. Instead they allow the user to
choose between up to 8 different output divider selections
depending on the clock and package configuration. This is
illustrated in the following Frequency Selection tables and
Functional Block Diagram.
There is one programmable OE/PDWN. The OE/PDWN pin
can be programmed as either an output enable pin or a
power-down pin. The OE function can be programmed to
disable a selected set of outputs when low, leaving the
remaining outputs running. Full-chip power down will disable
all outputs as well as the PLLs and most of the active circuitry
when low.
Factory-Programmable CY22388/89/91
Factory programming is available for high- or low-volume
manufacturing by Cypress. All requests must be submitted to
the local Cypress Field Application Engineer (FAE) or sales
representative. Once the request has been processed, you will
receive a new part number, samples, and data sheet with the
programmed values. This part number will be used for
additional sample requests and production orders.
PLLs
The advantage of having four PLLs is that a single device can
generate up to four independent frequencies from a single
crystal. Generally a design may require up to four oscillators
to accomplish what could be done with a single CY22388.
Each PLL is independent and can be configured to generate
a VCO (Voltage Controlled Oscillator) frequency between
62.5 MHz and 250 MHz. Each PLL can then in turn be divided
down with post dividers to generate the clock output frequency
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output to be divided by 1,2,3,4,5,6,8,9,10,12,15. The PLL
maximum is reduced to 166 MHz in divide by 1 mode due to
output buffer limitations.
Outputs that allow frequency switching perform the transition
free of glitches. A glitch is defined as a high or low time shorter
than half the smaller of the two periods being switched
between. Extended low time (even many cycles in duration) is
acceptable.
Selected clock outputs are capable of being powered off a
separate 2.5V supply. This will allow for driving lower voltage
swing inputs. The CY22388/89/91 device still requires 3.3V to
power the oscillator and all other internal PLL circuitry. For the
2.5V output option please refer to the CY22388 Application
Note. Selected clocks and pinout diagrams will be explained
in this application note.
Clock D can obtain its output from either the reference source
or PLL1/N1 with N1 being defined as the output divider for
PLL1. Clock H is defined as a copy of clock D. Clock D is only
available from PLL1/N1 on the 16-pin package.
For CY22388, CLKB and CLKC have related frequencies. For
CY22389 and CY22391, CLKD and CLKF have related
frequencies, CLKA and CLKB have related frequencies, and
Pin Description
Pin Name
Pin Number
Pin Description
16-Pin TSSOP 20-Pin TSSOP
32-Pin QFN
XIN
1
1
30
Crystal Input or Reference Clock Input
XOUT
16
20
27
Crystal Output (No connect if external clock is used)
CLKA
7
9
11
Clock Output
CLKB
8
8
10
Clock Output
CLKC
9
10
14
Clock Output
CLKD
10
7
9
Clock Output
CLKE
11
11
15
Clock Output
CLKF
n/a
12
17
Clock Output
CLKG
n/a
13
18
Clock Output
CLKH
n/a
4
8
Clock Output
FS0
2
2
31
Frequency Select 0
FS1
3
3
32
Frequency Select 1
FS2
14
17
23
Frequency Select 2
OE/PD
n/a
18
24
Output Enable Control/Power Down
VIN
4
16
1
Analog Control Input for VCXO
VDD
5,13,15
5,15,19
2,3,16,21,22,25,26
Voltage Supply
VSS
6,12
6,14
4,5,6,7,19,20
Ground
NC
n/a
n/a
12,13,28,29
No Connect.
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