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CY22388 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. CY22388
Description  Factory Programmable Quad PLL Clock Generator with VCXO
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY22388 Datasheet(HTML) 6 Page - Cypress Semiconductor

 
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CY22388/89/91
Document #: 38-07734 Rev. *B
Page 6 of 10
DC Parameters[4]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
IOH
[5]
Output High Current
VOH = VDD –0.
5,V
DD = 3.3V
12
mA
IOL
[5]
Output Low Current
VOL = 0.5, VDD = 3.3V
12
mA
IIH
Input High Current
VIH = VDD, excluding Vin, Xin
5
10
µA
IIL
Input Low Current
VIL = 0V, excluding Vin, Xin
5
10
µA
VIH
Input High Voltage
FS0/1/2 OE input CMOS levels
0.7xAVDD
V
VIL
Input Low Voltage
FS0/1/2 OE input CMOS levels
– 0.3xA
VDD
V
VVCXO
VIN Input Range
0
AVDD
V
CIN
Input Capacitance
FS0/1/2 and OE Pins only
7
pF
IVDD
Supply Current
VDD/AVDD/VDDL Current
60
mA
CINXIN
Input Capacitance at XIN VCXO Disabled External Reference
15
pF
CINXTAL
Input Capacitance at
Crystal
VCXO Disabled Fixed Freq. Oscillator
12
pF
Notes
4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
5. Custom Drive level and is available upon request
AC Parameters
Parameter[4]
Description
Conditions
Min.
Typ. Max. Units
1/t1
Output Frequency
PLL minmax/Dividermaximum
4.2
166
MHz
DC1
Output Duty Cycle
(excluding REFOUT
Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD
External reference duty cycle between 40% and 60% measured at
VDD/2 (Clock output is
125 MHz)
45
50
55
%
DC2
Output Duty Cycle
Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD
External reference duty cycle between 40% and 60% measured at
VDD/2 (Clock output is
125 MHz)
40
50
60
%
DCREFOUT
Output Duty Cycle
Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD
(XIN Duty Cycle = 45/55%)
40
50
60
%
ER
Rising Edge Rate
Output Clock Edge Rate. Measured from 20% to 80% of
VDD. CLOAD = 15 pF. See Figure 5.
0.75
1.2
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate. Measured from 80% to 20% of
VDD. CLOAD = 15pF See Figure 5.
0.75
1.2
V/ns
T9
Clock Jitter
Period Jitter
±250
ps
T10
PLL Lock Time
1
5
ms
fXO
VCXO Crystal Pull
Range
Using non-
SMD-49 crystal specified in
CY22388Appl
i
cat
i
on
Not
e,ANC0002”
Nominal Crystal Frequency Input assumed (0 ppm)@25°C and 3.3V
±110 ±120
ppm
Using
SMD-49 crystal specified in
CY22388Appl
i
cat
i
on
Not
e,ANC0002”
Nominal Crystal Frequency Input assumed (0 ppm)@25°C and 3.3V
±105 ±120
ppm
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