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CY22180 Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY22180
Description  Very Low Jitter Field and Factory Programmable Clock Generator
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY22180 Datasheet(HTML) 5 Page - Cypress Semiconductor

   
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PRELIMINARY
CY22180
Document #: 001-15577 Rev. **
Page 5 of 8
TPJ3
[2, 3]
CLKOUT pk-pk Period
Jitter, REFOUT on
CLKOUT = 20–200 MHz
150
(±75)
–ps
TPJ4
[2, 3]
REFOUT pk-pk Period Jitter REFOUT = 10-133 MHz
265
(±133)
ps
tSTP
Power Down Time
(pin 3 = PD#)
Time from falling edge on PD# to stopped outputs
(Asynchronous)
150
350
ns
TOE1
Output Disable Time
(pin 3 = OE)
Time from falling edge on OE to stopped outputs
(Asynchronous)
150
350
ns
TOE2
Output Enable Time
(pin 3 = OE)
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
150
350
ns
tPU1
Power Up Time,
Crystal is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–3.5
5
ms
tPU2
Power Up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous), reference clock at
correct frequency
–2
3
ms
AC Electrical Characteristics[1]
Parameter
Description
Condition
Min
Typ
Max
Unit
Notes
4. Since the load capacitors (CXIN and CXOUT) are provided by the CY22180, no external capacitors are needed on the XIN and XOUT pins to match the crystal
load capacitor (CL). Only a single 0.1-μF bypass capacitor is required on the VDD pin.
5. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
Application Circuits[4, 5]
0.1uF
VDD or
control
1
3
2
4
5
6
7
8
XIN/CLKIN
VDD
PD#/OE
VSS
REFOUT
CLKOUT
NC
XOUT
Power
CY22180
Crystal
no
connect
0.1uF
1
3
2
4
5
6
7
8
XIN/CLKIN
VDD
PD#/OE
VSS
REFOUT
CLKOUT
NC
XOUT
Power
CY22180
CLKIN
no
connect
no
connect
VDD or
control


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