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CY22180 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY22180
Description  Very Low Jitter Field and Factory Programmable Clock Generator
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY22180 Datasheet(HTML) 4 Page - Cypress Semiconductor

   
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PRELIMINARY
CY22180
Document #: 001-15577 Rev. **
Page 4 of 8
l
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
IOH
Output High Current
VOH = VDD – 0.5V, VDD = 3.3V (source)
10
12
mA
IOL
Output Low Current
VOL = 0.5V, VDD = 3.3V (sink)
10
12
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7VDD
–VDD + 0.3
V
VIL
Input Low Voltage
CMOS levels, 30% of VDD
–0.3
0.3VDD
V
IIH
Input High Current, PD#/OE VIN= VDD
––
10
μA
IIL
Input Low Current, PD#/OE VIN = VSS, pull up disabled
10
μA
VIN = VSS, pull up enabled
55
μA
IOZ
Output Leakage Current
Three-state output, PD#/OE = 0
–10
10
μA
CXIN or CXOUT
[1] Programmable Capacitance
at pin 1 and pin 8
Capacitance at minimum setting
12
pF
Capacitance at maximum setting
60
pF
CIN
[1]
Input Capacitance at
PD#/OE
–5
7
pF
IDD
Supply Current
fIN = 10 MHz, fOUT = 33 MHz, REFOUT off
11
15
mA
IDDS
Standby current
Device powered down with PD# = 0V (driven
reference pulled down)
–10
40
μA
AC Electrical Characteristics[1]
Parameter
Description
Condition
Min
Typ
Max
Unit
DC
Output Duty Cycle
CLKOUT < 125 MHz, Measured at VDD/2
45
50
55
%
Output Duty Cycle
CLKOUT > 125 MHz, Measured at VDD/2
40
50
60
%
Output Duty Cycle
REFOUT, Measured at VDD/2
Duty Cycle of CLKIN = 50%
45
50
55
%
SR1
Rising Edge Slew Rate
CLKOUT from 20 to 200 MHz;
REFOUT from 10 to 133 MHz. 20%–80% of VDD
23
V/ns
SR2
Falling Edge Slew Rate
CLKOUT from 20 to 200 MHz;
REFOUT from 10 to 133 MHz. 80%–20% of VDD
23
V/ns
TPJ1
[2, 3]
CLKOUT pk-pk Period
Jitter, REFOUT off
CLKOUT = 20–200 MHz
75
(±38)
ps
TPJ2
[2, 3]
CLKOUT pk-pk Period
Jitter, REFOUT off, specific
frequencies
CLKIN = 10 MHz, CLKOUT = 20, 33, 66, 80,
106.25, 125, 133, or 200 MHz
––
60
(±30)
ps
CLKIN = 25 MHz, CLKOUT = 125 MHz
56
(±28)
ps
CLKIN = 30 MHz, CLKOUT = 33, 66, 80, 106.25,
125, or 133 MHz
––
62
(±31)
ps
CLKIN = 66 MHz, CLKOUT = 33 or 66 MHz
47
(±24)
ps
CLKIN = 66 MHz, CLKOUT = 80, 106.25, 125,
133, 166, or 200 MHz
––
68
(±34)
ps
CLKIN = 133 MHz, CLKOUT = 33, 66, or 80 MHz
68
(±34)
ps
CLKIN = 133 MHz,
CLKOUT = 125, 133, or 166 MHz
––
52
(±26)
ps
Notes
1. Guaranteed by characterization, not 100% tested.
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, temperature, and output
load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions”.
3. Cycle-to-Cycle Jitter (peak) is always less than Period Jitter (peak-to-peak). Peak-to-Peak Period Jitter is the difference between the shortest and longest
measured periods.


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