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CY2907 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part No. CY2907
Description  Single-PLL General Purpose EPROM Programmable Clock Generator
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY2907 Datasheet(HTML) 1 Page - Cypress Semiconductor

 
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Single-PLL General Purpose EPROM
Programmable Clock Generator
CY2907
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-07137 Rev. *A
Revised May 21, 2007
Features
• Single phase locked loop (PLL) architecture
• EPROM programmability
• Factory-programmable (CY2907, CY2907I) or
field-programmable (CY2907F, CY2907FI) device options
• Up to two configurable outputs
• Low skew, low jitter, high accuracy outputs
• Power management (power down, OE)
• Frequency select option
• Configurable 5V or 3.3V operation
• 8-pin or 14-pin SOIC packages
Benefits
• Generates a custom frequency from an external source
• Easy customization and fast turnaround
• Programming support available for all opportunities
• Provides clocking requirements from a single device
• Meets critical industry-standard timing requirements
• Supports low-power applications
• Up to 16 user-selectable frequencies
• Supports industry-standard design platforms
• Industry-standard packaging saves on board space
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY2907
2
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–130 MHz (5V)
500 kHz–100 MHz (3.3V)
Factory Programmable
Commercial Temperature
CY2907I
2
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
Factory Programmable
Industrial Temperature
CY2907F8
CY2907F14
2
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–100 MHz (5V)
500 kHz–80 MHz (3.3V)
Field Programmable
Commercial Temperature
CY2907F8I
CY2907F14I
2
10 MHz–25 MHz (external crystal)
1 MHz–30 MHz (reference clock)
500 kHz–90 MHz (5V)
500 kHz–66.66 MHz (3.3V)
Field Programmable
Industrial Temperature
XTALOUT
XTALIN
REFCLK
OSC.
1
2
3
4
5
6
7
10
9
8
11
14
13
12
Top View
S1
S2
S3
VSS
VSS
PD
XTALIN
S0
REFCLK
VDD
CLKA
OEA
OER
XTALOUT
CLKA
PLL
EPROM
Table
S0
S1
14-Pin SOIC
S2
S3
OER
Output
Multiplexer
and
Dividers
PD
1
2
3
4
5
8
7
6
S0
VSS
XTALIN
XTALOUT
REFCLK
VDD
CLKA
S1
8-Pin SOIC
Configuration
EPROM
and Test Logic
OEA
Logic Block Diagram
Pin Configurations
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