CY7C1561V18
CY7C1576V18
CY7C1563V18
CY7C1565V18
Document Number: 001-05384 Rev. *E
Page 8 of 28
0.45*ns from the rising edge of the input clock (K or K). In order
to maintain the internal logic, each read access must be allowed
to complete. Each read access consists of four 18-bit data words
and takes 2 clock cycles to complete. Therefore, read accesses
to the device can not be initiated on two consecutive K clock
rises. The internal logic of the device ignores the second read
request. Read accesses can be initiated on every other K clock
rise. Doing so pipelines the data flow such that data is transferred
out of the device on every rising edge of the input clocks (K and
K).
When the Read Port is deselected, the CY7C1563V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the Positive Input Clock (K). This allows for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit Write Data Register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the Negative
Input Clock (K) the information presented to D[17:0] is also stored
into the Write Data Register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the Positive Input Clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
When deselected, the Write Port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1563V18. A
write operation is initiated as described in the “Write Operations”
section above. The bytes that are written are determined by
BWS0 and BWS1, which are sampled with each set of 18-bit data
words. Asserting the appropriate Byte Write Select input during
the data portion of a write allows the data being presented to be
latched and written into the device. Deasserting the Byte Write
Select input during the data portion of a write allows the data
stored in the device for that byte to remain unaltered. This feature
can be used to simplify Read/Modify/Write operations to a Byte
Write operation.
Concurrent Transactions
The Read and Write Ports on the CY7C1563V18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user can
read or write to any location, regardless of the transaction on the
other port. If the ports access the same location when a read
follows a write in successive clock cycles, the SRAM delivers the
most recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the
Read Port takes priority. If a read was initiated on the previous
cycle, the Write Port assumes priority (since read operations can
not be initiated on consecutive cycles). If a write was initiated on
the previous cycle, the Read Port assumes priority (since write
operations can not be initiated on consecutive cycles).
Therefore, asserting both port selects active from a deselected
state results in alternating read and write operations being
initiated, with the first access being a read.
Depth Expansion
The CY7C1563V18 has a port select input for each port. This
allows for easy depth expansion. Both port selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
Ω and 350Ω, with VDDQ =1.5V. The
output impedance is adjusted every 1024 cycles upon powerup
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free running clocks and are
synchronized to the input clock of the QDR-II+. The timings for
the echo clocks are shown in “Switching Characteristics” on
page 22.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with Data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30ns. However, it is not necessary for the DLL to be
reset in order to lock to the desired frequency. During Power up,
when the DOFF is tied HIGH, the DLL gets locked after 2048
cycles of stable clock.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
