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PRELIMINARY
CY14B256L
Document #: 001-06422 Rev. *E
Page 9 of 17
AC Switching Characteristics
Parameter
Description
25 ns part
35 ns part
45 ns part
Unit
Min
Max
Min
Max
Min
Max
Cypress
Parameter
Alt.
Parameter
SRAM READ Cycle
tACE
tACS
Chip Enable Access Time
25
35
45
ns
tRC [8]
tRC
Read Cycle Time
25
35
45
ns
tAA [9]
tAA
Address Access Time
25
35
45
ns
tDOE
tOE
Output Enable to Data Valid
12
15
20
ns
tOHA [9]
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE [10]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE [10]
tHZ
Chip Disable to Output Inactive
10
13
15
ns
tLZOE [10]
tOLZ
Output Enable to Output Active
0
0
0
ns
tHZOE [10]
tOHZ
Output Disable to Output Inactive
10
13
15
ns
tPU [7]
tPA
Chip Enable to Power Active
0
0
0
ns
tPD [7]
tPS
Chip Disable to Power Standby
25
35
45
ns
SRAM WRITE Cycle
tWC
tWC
Write Cycle Time
25
35
45
ns
tPWE
tWP
Write Pulse Width
20
25
30
ns
tSCE
tCW
Chip Enable To End of Write
20
25
30
ns
tSD
tDW
Data Setup to End of Write
10
12
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
20
25
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
ns
tHZWE [10, 11]
tWZ
Write Enable to Output Disable
10
13
15
ns
tLZWE [10]
tOW
Output Active after End of Write
3
3
3
ns
Notes
8. WE must be HIGH during SRAM READ Cycles.
9. Device is continuously selected with CE and OE both Low.
10. Measured ± 200 mV from steady state output voltage.
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