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CY7C1416AV18-300BZXI Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1416AV18-300BZXI
Description  36-Mbit DDR-II SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1416AV18-300BZXI Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Document Number: 38-05616 Rev. *D
Page 8 of 28
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the Write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments
the address in a linear fashion. On the following K clock rise
the data presented to D[17:0] is latched and stored into the
18-bit Write Data register provided BWS[1:0] are both asserted
active. On the subsequent rising edge of the Negative Input
Clock (K) the information presented to D[17:0] is also stored
into the Write Data register provided BWS[1:0] are both
asserted active. The 36 bits of data are then written into the
memory array at the specified location. Write accesses can be
initiated on every rising edge of the positive input clock (K).
Doing so will pipeline the data flow such that 18 bits of data
can be transferred into the device on every rising edge of the
input clocks (K and K).
When Write access is deselected, the device will ignore all
inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1427AV18.
A Write operation is initiated as described in the Write Opera-
tions section above. The bytes that are written are determined
by BWS0 and BWS1 which are sampled with each set of 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a Write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1427AV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
DDR Operation
The CY7C1427AV18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double data rate mode of operation. The CY7C1427AV18
requires a single No Operation (NOP) cycle when transitioning
from a Read to a Write cycle. At higher frequencies, some
applications may require a second NOP cycle to avoid
contention.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The Write information must be
stored because the SRAM cannot perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
If a Read is performed on the same address on which a Write
is performed in the previous cycle, the SRAM reads out the
most current data. The SRAM does this by bypassing the
memory array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175
Ω and 350Ω, with
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output clock
of the DDR-II. In the single clock mode, CQ is generated with
respect to K and CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF pin. For information
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
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