PRELIMINARY
CY14B256K
Document Number: 001-06431 Rev. *E
Page 5 of 23
Noise Considerations
The CY14B256K is a high-speed memory and so must have
a high-frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals will reduce circuit
noise.
Low Average Active Power
CMOS technology provides CY14B256K which allows
drawing less current when it is cycled at times longer than 50
ns. Figure 2 shows the relationship between ICC and READ
and/or WRITE cycle time. Worst case current consumption is
shown for commercial temperature range, VCC = 3.45V, and
chip enable at maximum frequency. Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the CY14B256K depends on the following items:
1. 1The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. IO loading.
Real-Time-Clock Operation
nvTIME Operation
The CY14B256K consists of internal registers that contain
clock, alarm, watchdog, interrupt, and control functions.
Internal double buffering of the clock and the clock/timer
information registers prevents accessing transitional internal
clock data during a read or write operation. Double buffering
also circumvents disrupting normal timing counts or clock
accuracy of the internal clock while accessing clock data.
Clock and Alarm Registers store data in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in one
second increments. The user can set the time to any calendar
time and the clock automatically keeps track of days of the
week and month, leap years, and century transitions. There
are eight registers dedicated to the clock functions that are
used to set time with a write cycle and to read time during a
read cycle. These registers contain the time of day in BCD
format. Bits defined as 0 are currently not used and are
reserved for future use by Cypress.
Reading the Clock
While the double buffered RTC register structure reduces the
chance of reading incorrect data from the clock, you to halt
internal updates to the CY14B256K clock registers before
reading clock data to prevent the reading of data in transition.
Stopping the internal register updates does not affect clock
accuracy. The update process is stopped by writing a 1 to the
read bit R (in the flags register at 0x7FF0), and will not restart
until a 0 is written to the read bit. The RTC registers can then
be read while the internal clock continues to run. Within 20 ms
after a 0 is written to the read bit, all CY14B256K registers are
simultaneously updated.
Setting the Clock
Setting the write bit W (in the flags register at 0x7FF0) to a 1
stops updates to the CY14B256K registers. The correct day,
date, and time can then be written into the registers in 24 hour
BCD format. The time written is referred to as the Base Time.
This value is stored in nonvolatile registers and used in
calculation of the current time. Resetting the write bit to 0
transfers those values to the actual clock counters, after which
the clock resumes normal operation.
Backup Power
The RTC in the CY14B256K is used for permanently powered
operation. Either the VRTCcap or VRTCbat pin is connected
depending on whether a capacitor or battery is chosen for the
application. When primary power, VCC, fails and drops below
VSWITCH the device will switch to the backup power supply.
The clock oscillator uses very little current, which maximizes
the backup time available from the backup source. Regardless
of clock operation with the primary source removed, the data
stored in nvSRAM is secure, having been stored in the
nonvolatile elements as power was lost.
During backup operation the CY14B256K consumes a
maximum of 300 nA at 2V. Capacitor or battery values must
be chosen according to the application. Backup time values
based on maximum current specs are shown in Table 2, RTC
Backup Time. Nominal times are approximately 3 times longer.
Using a capacitor has the advantage of recharging the backup
source each time the system is powered up. If a battery is
used, a 3V lithium is recommended and the CY14B256K will
Figure 2. Current vs. Cycle Time
Table 2. RTC Backup Time
Capacitor Value
Backup Time
0.1F
72 hours
0.47F
14 days
1.0F
30 days
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