CY8CLED16
Document Number: 001-13105 Rev. **
Page 9 of 39
Pin Information
Pinouts
The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled
with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No.
Type
Pin
Name
Description
28-Pin Device
Digital
Analog
1
IO
I
P0[7]
Analog column mux input.
2
IO
IO
P0[5]
Analog column mux input and column output.
3
IO
IO
P0[3]
Analog column mux input and column output.
4
IO
I
P0[1]
Analog column mux input.
5
IO
P2[7]
6
IO
P2[5]
7
IO
I
P2[3]
Direct switched capacitor block input.
8
IO
I
P2[1]
Direct switched capacitor block input.
9
Power
SMP
Switch Mode Pump (SMP) connection to
external components required.
10
IO
P1[7]
I2C Serial Clock (SCL).
11
IO
P1[5]
I2C Serial Data (SDA).
12
IO
P1[3]
13
IO
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
14
Power
Vss
Ground connection.
15
IO
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
16
IO
P1[2]
17
IO
P1[4]
Optional External Clock Input (EXTCLK).
18
IO
P1[6]
19
Input
XRES
Active high external reset with internal pull
down.
20
IO
I
P2[0]
Direct switched capacitor block input.
21
IO
I
P2[2]
Direct switched capacitor block input.
22
IO
P2[4]
External Analog Ground (AGND).
23
IO
P2[6]
External Voltage Reference (VREF).
24
IO
I
P0[0]
Analog column mux input.
25
IO
IO
P0[2]
Analog column mux input and column output.
26
IO
IO
P0[4]
Analog column mux input and column output.
27
IO
I
P0[6]
Analog column mux input.
28
Power
Vdd
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I,
P2[3]
A, I, P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
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