February 15, 2007
Document No. 38-12018 Rev. *J
3
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
PSoC® Overview
Analog blocks are arranged in a column of three, which
includes one CT (Continuous Time) and two SC (Switched
Capacitor) blocks, as shown in the figure below.
Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports 0-
5. Pins can be connected to the bus individually or in any com-
bination. The bus also connects to the analog system for analy-
sis with comparators and analog-to-digital converters. It can be
split into two sections for simultaneous dual-channel process-
ing. An additional 8:1 analog input multiplexer provides a sec-
ond path to bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge continu-
ously under hardware control. This enables capacitive mea-
surement for applications such as touch sensing. Other
multiplexer applications include:
■ Track pad, finger sensing.
■ Chip-wide mux that allows analog input from up to 48 IO
pins.
■ Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the lat-
est signal-to-noise signal level requirements Application Notes,
which can be found under http://www.cypress.com >> DESIGN
RESOURCES >> Application Notes. In general, and unless oth-
erwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Additional System Resources
System Resources, provide additional capability useful to com-
plete systems. Additional resources include a multiplier, deci-
mator, low voltage detection, and power on reset. Brief
statements describing the merits of each resource follow.
■ Full-Speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature
USB operation (-10°C to +85°C).
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
■ Two multiply accumulates (MACs) provide fast 8-bit multipli-
ers with 32-bit accumulate, to assist in both general math as
well as digital filters.
■ Decimator provides a custom hardware filter for digital signal
processing apps. including creation of Delta Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, multi-master are supported.
■ Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels, while the advanced POR (Power On
Reset) circuit eliminates the need for a system supervisor.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■ Versatile analog multiplexer system.
ACB00
ACB01
Block
Array
Array Input
Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Gene rators
AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Digital System
M 8C Interface (Address Bus, Data Bus, Etc.)
AnalogReference
All IO
(Exce pt Port 7)
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