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PRELIMINARY
CY7C1516AV18
CY7C1527AV18
CY7C1518AV18
CY7C1520AV18
Document #: 001-06982 Rev. *B
Page 2 of 28
Logic Block Diagram (CY7C1516AV18)
CLK
A(21: 0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS[1 : 0]
VREF
8
C
C
8
LD
Control
22
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
Logic Block Diagram (CY7C1527AV18)
CLK
A(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Data Reg.
R/W
DQ[8: 0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS[0]
VREF
9
C
C
9
LD
Control
22
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
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