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CY8C24994-24LFXI Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY8C24994-24LFXI
Description  PSoC짰 Mixed-Signal Array
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C24994-24LFXI Datasheet(HTML) 10 Page - Cypress Semiconductor

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February 15, 2007
Document No. 38-12018 Rev. *J
10
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.2
56-Pin Part Pinout (with XRES)
Table 1-2. 56-Pin Part Pinout (QFN**)
Pin
No.
Type
Name
Description
CY8C24894 56-Pin PSoC Device
Digital Analog
1
IO
I, M
P2[3]
Direct switched capacitor block input.
2
IO
I, M
P2[1]
Direct switched capacitor block input.
3
IO
M
P4[7]
4
IO
M
P4[5]
5
IO
M
P4[3]
6
IO
M
P4[1]
7
IO
M
P3[7]
8
IO
M
P3[5]
9
IO
M
P3[3]
10
IO
M
P3[1]
11
IO
M
P5[7]
12
IO
M
P5[5]
13
IO
M
P5[3]
14
IO
M
P5[1]
15
IO
M
P1[7]
I2C Serial Clock (SCL).
16
IO
M
P1[5]
I2C Serial Data (SDA).
17
IO
M
P1[3]
18
IO
M
P1[1]
I2C Serial Clock (SCL), ISSP SCLK*.
19
Power
Vss
Ground connection.
20
USB
D+
21
USB
D-
22
Power
Vdd
Supply voltage.
23
IO
P7[7]
24
IO
P7[0]
25
IO
M
P1[0]
I2C Serial Data (SDA), ISSP SDATA*.
26
IO
M
P1[2]
27
IO
M
P1[4]
28
IO
M
P1[6]
29
IO
M
P5[0]
Pin
No.
Type
Name
Description
30
IO
M
P5[2]
Digital Analog
31
IO
M
P5[4]
44
IO
M
P2[6]
External Voltage Reference (VREF) input.
32
IO
M
P5[6]
45
IO
I, M
P0[0]
Analog column mux input.
33
IO
M
P3[0]
46
IO
I, M
P0[2]
Analog column mux input.
34
IO
M
P3[2]
47
IO
I, M
P0[4]
Analog column mux input VREF.
35
IO
M
P3[4]
48
IO
I, M
P0[6]
Analog column mux input.
36
Input
XRES
Active high external reset with internal
pull down.
49
Power
Vdd
Supply voltage.
37
IO
M
P4[0]
50
Power
Vss
Ground connection.
38
IO
M
P4[2]
51
IO
I, M
P0[7]
Analog column mux input,.
39
IO
M
P4[4]
52
IO
IO, M
P0[5]
Analog column mux input and column output.
40
IO
M
P4[6]
53
IO
IO, M
P0[3]
Analog column mux input and column output.
41
IO
I, M
P2[0]
Direct switched capacitor block input.
54
IO
I, M
P0[1]
Analog column mux input.
42
IO
I, M
P2[2]
Direct switched capacitor block input.
55
IO
M
P2[7]
43
IO
M
P2[4]
External Analog Ground (AGND) input.
56
IO
M
P2[5]
LEGEND
A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
QFN
(Top View)
A, I, M, P2[3]
A, I, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
42
41
40
39
38
37
36
35
34
33
32
31
30
29
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