December 11, 2006
Document No. 38-12026 Rev. *D
2
CY8C29x66 Automotive Data Sheet
PSoC® Overview
processor. The CPU utilizes an interrupt controller with 25 vec-
tors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory includes 32K of Flash for program storage and 2K of
SRAM for data storage. Program Flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock genera-
tors, including a 24 MHz IMO (internal main oscillator) accurate
to 4% over temperature and voltage. A low power 32 kHz ILO
(internal low speed oscillator) is provided for the Sleep timer
and WDT. If crystal accuracy is desired, the ECO (32.768 kHz
external crystal oscillator) is available for use as a Real Time
Clock (RTC) and can optionally generate a crystal-accurate 24
MHz system clock using a PLL. The clocks, together with pro-
grammable clock dividers (as a System Resource), provide the
flexibility to integrate almost any timing requirement into the
PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external interfac-
ing. Every pin also has the capability to generate a system inter-
rupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 16 digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or com-
bined with other blocks to form 8, 16, 24, and 32-bit peripherals,
which are called user module references. Digital peripheral con-
figurations include those listed below.
■
PWMs (8 to 32 bit)
■
PWMs with Dead Band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity (up to 4)
■
SPI Master and Slave (up to 4 each)
■
I2C Slave and Multi-Master (1 available as a System
Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 4)
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the con-
straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the opti-
mum choice of system resources for your application. Family
resources are shown in the table titled “PSoC Device Charac-
teristics” on page 3.
Digital System Block Diagram
The Analog System
The Analog System is composed of 12 configurable blocks,
each comprised of an opamp circuit allowing the creation of
complex analog signal flows. Analog peripherals are very flexi-
ble and can be customized to support specific application
requirements. Some of the more common PSoC analog func-
tions (most available as user modules) are listed below.
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-
tion, selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to
93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 40 mA drive as a PSoC
Core resource)
■
1.3V reference (as a System Resource)
■
DTMF Dialer
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
8
8
8
Row 1
DBB10
DBB11
DCB12
DCB13
4
4
Row 2
DBB20
DBB21
DCB22
DCB23
4
4
Row 0
DBB00
DBB01
DCB02
DCB03
4
4
Row 3
DBB30
DBB31
DCB32
DCB33
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
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