72-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
CY7C1541V18
CY7C1556V18
CY7C1543V18
CY7C1545V18
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-05389 Rev. *E
Revised July 24, 2007
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 375 MHz clock for high bandwidth
■ 4-Word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both Read and Write
Ports (data transferred at 750 MHz) at 375 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Single multiplexed address input bus latches address inputs
for both Read and Write Ports
■ Separate Port Selects for depth expansion
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD
[1]
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1541V18 – 8M x 8
CY7C1556V18 – 8M x 9
CY7C1543V18 – 4M x 18
CY7C1545V18 – 2M x 36
Functional Description
The CY7C1541V18, CY7C1556V18, CY7C1543V18, and
CY7C1545V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II+ architecture. Similar to QDR-II archi-
tecture, QDR-II+ SRAMs consists of two separate ports to
access the memory array. The Read Port has dedicated Data
Outputs to support read operations and the Write Port has
dedicated Data Inputs to support write operations. QDR-II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common IO devices. Access to each port is accom-
plished through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II+ Read and Write Ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write Ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1541V18), 9-bit words
(CY7C1556V18), 18-bit words (CY7C1543V18), or 36-bit words
(CY7C1545V18) that burst sequentially into or out of the device.
Since data can be transferred into and out of the device on every
rising edge of both input clocks (K and K), memory bandwidth is
maximized while simplifying system design by eliminating bus
“turn-arounds”.
Depth expansion is accomplished with Port Selects for each port.
Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
375 MHz
333 MHz
300 MHz
Unit
Maximum Operating Frequency
375
333
300
MHz
Maximum Operating Current
x8
1300
1200
1100
mA
x9
1300
1200
1100
x18
1300
1200
1100
x36
1370
1230
1140
Note
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
VDDQ = 1.4V to VDD.
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