3 / 26 page
PRELIMINARY
CY7C1510AV18
CY7C1525AV18
CY7C1512AV18
CY7C1514AV18
Document #: 001-06984 Rev. *B
Page 3 of 26
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
950
850
800
mA
Logic Block Diagram (CY7C1512AV18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
18
36
18
BWS[1:0]
VREF
18
A(20:0)
21
C
C
18
Write
Reg
Write
Reg
CQ
CQ
18
DOFF
Logic Block Diagram (CY7C1514AV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
36
72
36
BWS[3:0]
VREF
36
A(19:0)
20
C
C
36
Write
Reg
Write
Reg
CQ
CQ
36
DOFF
[+] Feedback
[+] Feedback