February 15, 2007
Document No. 38-12018 Rev. *J
11
CY8C24094, CY8C24794, CY8C24894, and CY8C24994 Final Data Sheet
1. Pin Information
1.3
68-Pin Part Pinout
The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.
Table 1-3. 68-Pin Part Pinout (QFN**)
Pin
No.
Type
Name
Description
CY8C24994 68-Pin PSoC Device
Digital Analog
1
IO
M
P4[7]
2
IO
M
P4[5]
3
IO
M
P4[3]
4
IO
M
P4[1]
5
NC
No connection.
6
NC
No connection.
7
Power
Vss
Ground connection.
8
IO
M
P3[7]
9
IO
M
P3[5]
10
IO
M
P3[3]
11
IO
M
P3[1]
12
IO
M
P5[7]
13
IO
M
P5[5]
14
IO
M
P5[3]
15
IO
M
P5[1]
16
IO
M
P1[7]
I2C Serial Clock (SCL).
17
IO
M
P1[5]
I2C Serial Data (SDA).
18
IO
M
P1[3]
19
IO
M
P1[1]
I2C Serial Clock (SCL) ISSP SCLK*.
20
Power
Vss
Ground connection.
21
USB
D+
22
USB
D-
23
Power
Vdd
Supply voltage.
24
IO
P7[7]
25
IO
P7[6]
26
IO
P7[5]
27
IO
P7[4]
28
IO
P7[3]
29
IO
P7[2]
Pin
No.
Type
Name
Description
30
IO
P7[1]
Digital
Analog
31
IO
P7[0]
50
IO
M
P4[6]
32
IO
M
P1[0]
I2C Serial Data (SDA), ISSP SDATA*.
51
IO
I,M
P2[0]
Direct switched capacitor block input.
33
IO
M
P1[2]
52
IO
I,M
P2[2]
Direct switched capacitor block input.
34
IO
M
P1[4]
Optional External Clock Input (EXT-
CLK).
53
IO
M
P2[4]
External Analog Ground (AGND) input.
35
IO
M
P1[6]
54
IO
M
P2[6]
External Voltage Reference (VREF) input.
36
IO
M
P5[0]
55
IO
I,M
P0[0]
Analog column mux input.
37
IO
M
P5[2]
56
IO
I,M
P0[2]
Analog column mux input and column output.
38
IO
M
P5[4]
57
IO
I,M
P0[4]
Analog column mux input and column output.
39
IO
M
P5[6]
58
IO
I,M
P0[6]
Analog column mux input.
40
IO
M
P3[0]
59
Power
Vdd
Supply voltage.
41
IO
M
P3[2]
60
Power
Vss
Ground connection.
42
IO
M
P3[4]
61
IO
I,M
P0[7]
Analog column mux input, integration input #1
43
IO
M
P3[6]
62
IO
IO,M
P0[5]
Analog column mux input and column output, integra-
tion input #2.
44
NC
No connection.
63
IO
IO,M
P0[3]
Analog column mux input and column output.
45
NC
No connection.
64
IO
I,M
P0[1]
Analog column mux input.
46
Input
XRES
Active high pin reset with internal pull
down.
65
IO
M
P2[7]
47
IO
M
P4[0]
66
IO
M
P2[5]
48
IO
M
P4[2]
67
IO
I,M
P2[3]
Direct switched capacitor block input.
49
IO
M
P4[4]
68
IO
I,M
P2[1]
Direct switched capacitor block input.
LEGEND
A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
QFN
(Top View)
[+] Feedback
[+] Feedback