EZ-USB FX2LP™ USB Microcontroller
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-08032 Rev. *K
Revised January 26, 2006
1.0
Features (CY7C68013A/14A/15A/16A)
• USB 2.0–USB-IF high speed certified (TID # 40440111)
• Single-chip integrated USB 2.0 transceiver, smart SIE,
and enhanced 8051 microprocessor
• Fit, form and function compatible with the FX2
— Pin-compatible
— Object-code-compatible
— Functionally-compatible (FX2LP is a superset)
• Ultra Low power: ICC no more than 85 mA in any mode
— Ideal for bus and battery powered applications
• Software: 8051 code runs from:
— Internal RAM, which is downloaded via USB
— Internal RAM, which is loaded from EEPROM
— External memory device (128 pin package)
• 16 KBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCHRO-
NOUS endpoints
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF (General Programmable Interface)
— Allows direct connection to most parallel interface
— Programmable waveform descriptors and configu-
ration registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
• Integrated, industry-standard enhanced 8051
— 48-MHz, 24-MHz, or 12-MHz CPU operation
— Four clocks per instruction cycle
— Two USARTS
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 3.3V operation with 5V tolerant inputs
• Vectored USB interrupts and GPIF/FIFO interrupts
• Separate data buffers for the Set-up and Data portions
of a CONTROL transfer
• Integrated I2C controller, runs at 100 or 400 kHz
• Four integrated FIFOs
— Integrated glue logic and FIFOs lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— Uses external clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Available in Commercial and Industrial temperature
grade (all packages except VFBGA)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I2C
VCC
1.5k
D+
D–
FX2LP
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full- and high-speed
XCVR
Additional I/Os (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes/s
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
Abundant I/O
including two USARTS
High-performance micro
using standard tools
with lower-power options
Master
Figure 1-1. Block Diagram
connected for
full speed
ECC
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