CY7C1464AV25-250BGXI datasheet(5/27 Pages) CYPRESS

Part #	CY7C1464AV25-250BGXI

Description	36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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5 / 27 page

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Document #: 38-05354 Rev. *D

Page 5 of 27

Pin Configurations (continued)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

12

3456789

11

10

DQg

DQc

NC

DQPg

DQh

DQd

DQPd

DQPc

DQc

NC

DQh

DQPh

DQd

DQb

DQf

NC

DQPf

DQa

DQe

DQPa

DQPb

DQf

NC

DQa

DQPe

DQe

A

AA

A

NC

NC/144M

NC/72M

A

NC/288M

A

AA

A

A1

A0

A

AA

A

NC/1G

NC/576M

NC

BWSb

BWSf

BWSe

BWSa

BWSc

BWSg

BWSd

BWSh

TMS

TDI

TDO

TCK

NC

MODE

NC

CEN

VSS

NC

CLK

NC

VSS

VDD

VSS

VDD

NC

OE

CE3

CE1

CE2

ADV/LD

WE

VSS

ZZ

VSS

NC

VDDQ

VSS

NC

VSS

NC

VSS

VDDQ

NC

VDDQ

NC

VDDQ

NC

VDDQ

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV25 (512K x 72)

Pin Definitions

Pin Name

I/O Type

Pin Description

A0

A1

A

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf

controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

WE

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

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CY7C1464AV25-250BGXI Datasheet(PDF) 5 Page - Cypress Semiconductor

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