Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1511V18-200BZC Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1511V18-200BZC
Description  72-Mbit QDR?? II SRAM 4-Word Burst Architecture
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1511V18-200BZC Datasheet(HTML) 1 Page - Cypress Semiconductor

  CY7C1511V18-200BZC Datasheet HTML 1Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 2Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 3Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 4Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 5Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 6Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 7Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 8Page - Cypress Semiconductor CY7C1511V18-200BZC Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 28 page
background image
72-Mbit QDR™- II SRAM 4-Word Burst
Architecture
CY7C1511V18
CY7C1526V18
CY7C1513V18
CY7C1515V18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document #: 38-05363 Rev. *D
Revised May 31, 2006
Features
• Separate Independent Read and Write Data Ports
— Supports concurrent transactions
• 300-MHz Clock for High Bandwidth
• 4-Word Burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 600 MHz) at 300 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency providing most current data
•Core VDD = 1.8 (±0.1V); I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 Compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1511V18 – 8M x 8
CY7C1526V18 – 8M x 9
CY7C1513V18 – 4M x 18
CY7C1515V18 – 2M x 36
Functional Description
The CY7C1511V18, CY7C1526V18, CY7C1513V18, and
CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array.
The Read port has dedicated Data Outputs to support Read
operations and the Write Port has dedicated Data Inputs to
support Write operations. QDR-II architecture has separate
data inputs and data outputs to completely eliminate the need
to “turn-around” the data bus required with common I/O
devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR-II Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 8-bit words (CY7C1511V18) or 9-bit
words (CY7C1526V18) or 18-bit words (CY7C1513V18) or
36-bit words (CY7C1515V18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K and
K and C and C), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
950
900
850
750
700
mA
[+] Feedback
[+] Feedback


Similar Part No. - CY7C1511V18-200BZC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1511V18-200BZC CYPRESS-CY7C1511V18-200BZC Datasheet
381Kb / 23P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
More results

Similar Description - CY7C1511V18-200BZC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1511KV18 CYPRESS-CY7C1511KV18_09 Datasheet
837Kb / 31P
   72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1561KV18 CYPRESS-CY7C1561KV18 Datasheet
833Kb / 28P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511V18 CYPRESS-CY7C1511V18 Datasheet
381Kb / 23P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1511JV18 CYPRESS-CY7C1511JV18 Datasheet
703Kb / 29P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C2561KV18 CYPRESS-CY7C2561KV18 Datasheet
845Kb / 29P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511KV18 CYPRESS-CY7C1511KV18_11 Datasheet
807Kb / 33P
   72-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1511AV18 CYPRESS-CY7C1511AV18 Datasheet
709Kb / 31P
   72-Mbit QDR??II SRAM 4-Word Burst Architecture
CY7C1513KV18 CYPRESS-CY7C1513KV18 Datasheet
831Kb / 31P
   72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1510KV18 CYPRESS-CY7C1510KV18_09 Datasheet
836Kb / 30P
   72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1510JV18 CYPRESS-CY7C1510JV18_09 Datasheet
654Kb / 26P
   72-Mbit QDR??II SRAM 2-Word Burst Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com