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CY7C1483V33-100AXI Datasheet(PDF) 11 Page - Cypress Semiconductor

Part # CY7C1483V33-100AXI
Description  72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1483V33-100AXI Datasheet(HTML) 11 Page - Cypress Semiconductor

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CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *H
Page 11 of 30
Truth Table for Read/Write
The read-write truth table for CY7C1481V33 follows.[3, 8]
Function
GW
BWE
BWD
BWC
BW
B
BWA
Read
H
H
X
X
X
X
Read
H
L
HHHH
Write Byte A (DQA, DQPA)
H
L
HHH
L
Write Byte B(DQB, DQPB)H
L
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)H
L
H
H
L
L
Write Byte C (DQC, DQPC)
H
LH
LH
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
H
LH
LHL
Write Bytes C, B (DQC, DQB, DQPC, DQPB)H
L
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA)H
L
H
L
L
L
Write Byte D (DQD, DQPD)
H
L
L
HHH
Write Bytes D, A (DQD, DQA, DQPD, DQPA)H
L
L
H
H
L
Write Bytes D, B (DQD, DQA, DQPD, DQPA)H
L
L
H
L
H
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA)H
L
L
H
L
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)H
L
L
L
H
H
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA)H
L
L
L
H
L
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA)H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Truth Table for Read/Write
The read-write truth table for CY7C1483V33 follows.[3, 8]
Function
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A - (DQA and DQPA)H
L
H
L
Write Byte B - (DQB and DQPB)H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
Truth Table for Read/Write
The read-write truth table for CY7C1487V33 follows.[3, 8]
Function
GW
BWE
BWx[9]
Read
H
H
X
Read
H
L
All BW = H
Write Byte x – (DQx and DQPx)H
L
L
Write All Bytes
H
L
All BW = L
Write All Bytes
L
X
X
Notes
8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. An appropriate write is performed based on which byte write is active.
9. BWx represents any byte write signal BWX.To enable any byte write BWx , a Logic LOW signal must be applied at clock rise. Any number of byte writes can be
enabled at the same time for any given write.
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