CY7C1561V18
CY7C1576V18
CY7C1563V18
CY7C1565V18
Document Number: 001-05384 Rev. *E
Page 7 of 28
Functional Overview
The CY7C1561V18, CY7C1576V18, CY7C1563V18, and
CY7C1565V18 are synchronous pipelined Burst SRAMs
equipped with both a Read Port and a Write Port. The Read Port
is dedicated to read operations and the Write Port is dedicated
to write operations. Data flows into the SRAM through the Write
Port and out through the Read Port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write Ports, the QDR-II+
completely eliminates the need to “turn-around” the data bus and
avoids any possible data contention, thereby simplifying system
design. Each access consists of four 8-bit data transfers in the
case of CY7C1561V18, four 9-bit data transfers in the case of
CY7C1576V18, four 18-bit data transfers in the case of
CY7C1563V18, and four 36-bit data transfers in the case of
CY7C1565V18, in two clock cycles.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the input clocks (K and
K) as well.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1563V18 is described in the following sections. The same
basic descriptions apply to CY7C1561V18, CY7C1576V18, and
CY7C1565V18.
Read Operations
The CY7C1563V18 is organized internally as 4 arrays of 1M x
18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
address presented to Address inputs are stored in the Read
Address Register. Following the next two K clock rise, the corre-
sponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the subse-
quent rising edge of K the next 18-bit data word is driven onto
the Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data is valid
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page 22.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
DOFF
Input
DLL Turn Off-Active LOW. Connecting this pin to ground turns off the DLL inside the device.The
timings in the DLL turned off operation are different from those listed in this data sheet. For normal
operation, this pin can be connected to a pull up through a 10 K
Ω or less pull up resistor. The device
behaves in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a
frequency of up to 167 MHz with QDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
IO
Pin Description
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