CY7C53150
CY7C53120
Document #: 38-10001 Rev. *E
Page 8 of 14
Notes
15. tcyc = 2(1/f), where f is the input clock (CLK1) frequency (20, 10, 5, 2.5, 1.25, or 0.625 MHz).
16. Refer to Figure 3 for detailed measurement information.
17. The data hold parameter, tDHW, is measured to the disable levels shown in Figure 5, rather than to the traditional data invalid levels.
18. Refer to Figure 6 and Figure 5 for detailed measurement information.
19. The three-state condition is when the device is not actively driving data. Refer to Figure 2 and Figure 5 for detailed measurement information.
20. To meet the timing above for 20-MHz operation, the loading on A0–A15, D0–D7, and R/W is 30 pF. Loading on E is 20 pF.
21. Common mode voltage is defined as the average value of the waveform at each input at the time switching occurs.
22. Z0 = |V[CP2]-V[CP3] |/40 mA for 4.75 < VDD < 5.25V.
External Memory Interface Timing — CY7C53150, VDD ± 10% (VDD = 4.5V to 5.5 V, TA = –40°C to+ 85°C
[2])
Parameter
Description
Min.
Max.
Unit
tcyc
Memory Cycle Time (System Clock Period)[15]
100
3200
ns
PWEH
Pulse Width, E High[16]
tcyc/2 – 5
tcyc/2 + 5
ns
PWEL
Pulse Width, E Low[16]
tcyc/2 – 5
tcyc/2 + 5
ns
tAD
Delay, E High to Address Valid[20]
—
35
ns
tAH
Address Hold Time After E High[20]
10
—
ns
tRD
Delay, E High to R/W Valid Read[20]
—
25
ns
tRH
R/W Hold Time Read After E High
5
—
ns
tWR
Delay, E High to R/W Valid Write
—
25
ns
tWH
R/W Hold Time Write After E High
5
—
ns
tDSR
Read Data Setup Time to E High
15
—
ns
tDHR
Data Hold Time Read After E High
0
—
ns
tDHW
Data Hold Time Write After E High[17, 18]
10
—
ns
tDDW
Delay, E Low to Data Valid
—
12
ns
tDHZ
Data Three State Hold Time After E Low[19]
0
—
ns
tDDZ
Delay, E High to Data Three-State[18]
—
42
ns
tacc
External Memory Access Time (tacc = tcyc – tAD – tDSR) at
20-MHz input clock
50
—
ns
Differential Transceiver Electrical Characteristics
Characteristic
Min.
Max.
Unit
Receiver Common Mode Voltage Range to maintain hysteresis[21]
1.2
VDD – 2.2
V
Receiver Common Mode Range to operate with unspecified hysteresis
0.9
VDD – 1.75
V
Input Offset Voltage
–0.05Vhys – 35
0.05Vhys + 35
mV
Propagation Delay (F = 0, VID = Vhys/2 + 200 mV)
—
230 ns
ns
Input Resistance
5
—
M
Ω
Wake-up Time
—
10
μs
Differential Output Impedance for CP2 and CP3[22]
35
Ω
TEST SIGNAL
CL
CL = 20 pF for E
CL = 30 pF for A0–A15, D0–D7, and R/W
CL = 50 pF for all other signals
Figure 2. Signal Loading for Timing Specifications Unless Otherwise Specified
PWEL
2.0V
PWEH
2.0V
0.8V
Figure 3. Test Point Levels for E Pulse Width Measurements
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