CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B
Page 2 of 51
TABLE OF CONTENTS
1.0 FEATURES .......................................................................................................................................6
2.0 FUNCTIONAL OVERVIEW ..............................................................................................................7
3.0 PIN CONFIGURATIONS ..................................................................................................................9
4.0 PRODUCT SUMMARY TABLES ...................................................................................................10
4.1 Pin Assignments ......................................................................................................................10
4.2 I/O Register Summary ...............................................................................................................10
4.3 Instruction Set Summary ...........................................................................................................12
5.0 PROGRAMMING MODEL ..............................................................................................................13
5.1 14-Bit Program Counter (PC) ....................................................................................................13
5.1.1 Program Memory Organization .......................................................................................................14
5.2 8-Bit Accumulator (A) ................................................................................................................15
5.3 8-Bit Temporary Register (X) ....................................................................................................15
5.4 8-Bit Program Stack Pointer (PSP) ...........................................................................................15
5.4.1 Data Memory Organization .............................................................................................................15
5.5 8-Bit Data Stack Pointer (DSP) .................................................................................................16
5.6 Address Modes .........................................................................................................................16
5.6.1 Data (Immediate) .............................................................................................................................16
5.6.2 Direct ...............................................................................................................................................16
5.6.3 Indexed ...........................................................................................................................................16
6.0 CLOCKING .....................................................................................................................................17
7.0 RESET ............................................................................................................................................17
7.1 Power-On Reset (POR) ............................................................................................................17
7.2 Watchdog Reset (WDR) ............................................................................................................17
8.0 SUSPEND MODE ...........................................................................................................................18
9.0 GENERAL-PURPOSE I/O (GPIO) PORTS ....................................................................................19
9.1 GPIO Configuration Port ...........................................................................................................20
9.2 GPIO Interrupt Enable Ports .....................................................................................................21
10.0 DAC PORT ...................................................................................................................................21
10.1 DAC Isink Registers ................................................................................................................22
10.2 DAC Port Interrupts .................................................................................................................23
11.0 12-BIT FREE-RUNNING TIMER ..................................................................................................23
12.0 I2C AND HAPI CONFIGURATION REGISTER ...........................................................................24
13.0 I2C-COMPATIBLE CONTROLLER ..............................................................................................25
14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ........................................................27
15.0 PROCESSOR STATUS AND CONTROL REGISTER .................................................................28
16.0 INTERRUPTS ...............................................................................................................................29
16.1 Interrupt Vectors ......................................................................................................................30
16.2 Interrupt Latency .....................................................................................................................31
16.3 USB Bus Reset Interrupt .........................................................................................................31
16.4 Timer Interrupt .........................................................................................................................31
16.5 USB Endpoint Interrupts .........................................................................................................31
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