72-Mbit (2M x 36/4M x 18) Pipelined
DCD Sync SRAM
CY7C1484V33
CY7C1485V33
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-05285 Rev. *G
Revised May 01, 2007
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 3.3V core power supply (VDD)
• 2.5V/3.3V IO operation
• Fast clock-to-output times
— 3.0 ns (for 250 MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1484V33
, CY7C1485V33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
Functional Description[1]
The CY7C1484V33/CY7C1485V33 SRAM integrates 2M x
36/4M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE1), depth-expansion Chip
Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BWX, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle. This part supports byte write
operations (see “Pin Definitions” on page 5 and “Truth Table”
on page 8 for further details). Write cycles can be one to four
bytes wide as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written. This device incor-
porates an additional pipelined enable register which delays
turning off the output buffers an additional cycle when a
deselect is executed.This feature enables depth expansion
without penalizing system performance.
The CY7C1484V33/CY7C1485V33 operates from a +3.3V
core power supply while all outputs operate with a +3.3V or a
+2.5V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Note
1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Access Time
3.0
3.0
3.4
ns
Maximum Operating Current
500
500
450
mA
Maximum CMOS Standby Current
120
120
120
mA
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