CY7C1444AV33
CY7C1445AV33
Document #: 38-05352 Rev. *E
Page 8 of 27
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1444AV33/CY7C1445AV33
supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486
™ processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous
Chip
Selects
CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
The CY7C1444AV33/CY7C1445AV33 is a double-cycle
deselect part. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will tri-state immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded
into
the
address
register
and
the
address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BWX) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BWX
signals. The CY7C1444AV33/CY7C1445AV33 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Because the CY7C1444AV33/CY7C1445AV33 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWX) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
–
No Connects. Not internally connected to the die. 72M, 144M, 288M, 576M and 1G are
address expansion pins are not internally connected to the die.
Pin Definitions (continued)
Name
I/O
Description
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
