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IDTRC5000 Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDTRC5000 Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 16 page IDT RC5000 COMMERCIAL TEMPERATURE RANGE 6 Pin Description RC5000 implements a bus similar to that of the RC4700. Table 2 lists and describes the RC5000 signals. Pin Name Type Description System interface: ExtRqst* Input External Request. Signals that the system interface needs to submit an external request. Release* Output Release Interface. Signals that the processor is releasing the system interface to slave state RdRdy* Input Read Ready. Signals that an external agent can now accept a processor read. WrRdy* Input Write Ready. Signals that an external agent can now accept a processor write request. ValidIn* Input Valid Input. Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com- mand or data identifier on the SysCmd bus. ValidOut* Output Valid Output. Signals that the processor is now driving a valid address or data on the SysAD bus and a valid com- mand or data identifier on the SysCmd bus. SysAD(63:0) Input/Output System Address/Data bus. A 64-bit address and data bus for communication between the processor and an external agent. SysADC(7:0) Input/Output System Address/Data check bus. An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles. SysCmd(8:0) Input/Output System Command/data identifier bus. A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmdP Input/Output Reserved System Command/data identifier bus parity. For the RC5000, unused on input and zero on output. Clock/control interface: SysClock Input Master Clock. Master clock input at the bus frequency. The pipeline clock is derived by multiplying this clock up. VCCP Input Quiet VCC for PLL. Quiet VCC for the internal phase locked loop. VSSP Input Quiet VSS for PLL. Quiet VSS for the internal phase locked loop. Interrupt interface: Int(5:0)* Input Interrupt. Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. NMI* Input Non-maskable interrupt. Non-maskable interrupt, ORed with bit 6 of the interrupt register. JTAG interface: JTDI Input JTAG Data In. Connected directly to JTDO. No JTAG implemented; should be pulled High. JTCK Input JTAG Clock Input. Unused input; should be pulled High. JTDO Output JTAG Data Out. Connected directly to JTDI. If no external scan used, this is a no connect. Table 2. RC5000 Signal Names and Descriptions (Page 1 of 2) |
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