5

1999

Integrated Device Technology, Inc.

©

IDT

IDT7M9510 / IDT7M9514

PMC CONNECTORS

The 7M9510 / 7M9514 utilizes three 64 position connectors that are

compliant with the PMC standard. The placement of these connectors is in

compliance with the Common Mezzanine Card (CMC) Specification (IEEE

1386) and the PCI Mezzanine Card (PMC) Specification (IEEE 1386.1).

Headers correspond as follows:

-J1 on the 7M9510 / 7M9514 corresponds to PN11 (PN1) and P12

(PN2) in the PMC and CMC Specifications.

-J2 on the 7M9510 / 7M9514 corresponds to P14 (PN4) in the PMC

and CMC Specifications.

For further information on the mechanical placement of the PMC

headers, refer to the Common Mezzanine Card (CMC) Specification (IEEE

1386).

PIN ASSIGNMENTS

The 32-bit bus is implemented in J1 (PN1 and PN2), in compliance with

the PMC Specifications and is provided below. The User-Defined I/O is

implemented in J2 (PN4) and is provided below.

1

N

P

#

n

i

Pe

m

a

N

l

a

n

g

i

Se

m

a

N

l

a

n

g

i

S#

n

i

P

1K

C

TV

2

1

-

)

1

(

2

3D

N

G#

A

T

N

I4

5#

B

T

N

I#

C

T

N

I6

7#

1

E

E

D

O

M

S

U

Bv

5

+8

9#

D

T

N

ID

V

S

R

-I

C

P

)

1

(

0

1

1

1D

N

GD

V

S

R

-I

C

P

)

1

(

2

1

3

1K

L

CD

N

G4

1

5

1D

N

G#

T

N

G6

1

7

1#

Q

E

RV

5

+8

1

9

1)

O

/I

(

V

)

1

(

]

1

3

[

D

A0

2

1

2]

8

2

[

D

A]

7

2

[

D

A2

2

3

2]

5

2

[

D

AD

N

G4

2

5

2D

N

G#

]

3

[

E

B

/

C6

2

7

2]

2

2

[

D

A]

1

2

[

D

A8

2

9

2]

9

1

[

D

AV

5

+0

3

1

3)

O

/I

(

V

)

1

(

]

7

1

[

D

A2

3

3

3#

E

M

A

R

FD

N

G4

3

5

3D

N

G#

Y

D

R

I6

3

7

3#

L

E

S

V

E

DV

5

+8

3

9

3D

N

G#

K

C

O

L0

4

1

4#

E

N

O

D

S

)

1

(

(

#

O

B

S

)

1

(

2

4

3

4R

A

PD

N

G4

4

5

4)

O

/I

(

V

)

1

(

]

5

1

[

D

A6

4

7

4]

2

1

[

D

A]

1

1

[

D

A8

4

9

4]

9

0

[

D

AV

5

+0

5

1

5D

N

G#

]

0

[

E

B

/

C2

5

3

5]

6

0

[

D

A]

5

0

[

D

A4

5

5

5]

4

0

[

D

AD

N

G6

5

7

5)

O

/I

(

V]

3

1

[

D

A8

5

9

5]

2

0

[

D

A]

1

0

[

D

A0

6

1

6]

0

0

[

D

AV

5

+2

6

3

6D

N

G#

4

6

Q

E

R4

6

NOTES:

1. Not connected on 7M9510 / 7M9514

4095 tbl 04

2

N

P

#

n

i

Pe

m

a

N

l

a

n

g

i

Se

m

a

N

l

a

n

g

i

S#

n

i

P

1V

2

1

+

)

1

(

#

T

S

R

T2

3S

M

TO

D

T4

5I

D

TD

N

G6

7D

N

GD

V

S

R

-I

C

P

)

1

(

8

9D

V

S

R

-I

C

P

)

1

(

D

V

S

R

-I

C

P

)

1

(

0

1

1

1#

2

E

D

O

M

S

U

B

)

1

(

V

3

.

3

+2

1

3

1#

T

S

R#

3

E

D

O

M

S

U

B4

1

5

1V

3

.

3

+#

4

E

D

O

M

S

U

B6

1

7

1D

V

S

R

-I

C

P

)

1

(

D

N

G8

1

9

1]

0

3

[

D

A]

9

2

[

D

A0

2

1

2D

N

G]

6

2

[

D

A2

2

3

2]

4

2

[

D

AV

3

.

3

+4

2

5

2L

E

S

D

I]

3

2

[

D

A6

2

7

2V

3

.

3

+]

0

2

[

D

A8

2

9

2]

8

1

]

D

AD

N

G0

3

1

3]

6

1

[

D

A#

]

2

[

E

B

/

C2

3

3

3D

N

GD

V

S

R

-

C

M

P

)

1

(

4

3

5

3#

Y

D

R

TV

3

.

3

+6

3

7

3D

N

G#

P

O

T

S8

3

9

3#

R

R

E

PD

N

G0

4

1

4V

3

.

3

+#

R

R

E

S2

4

3

4#

]

1

[

E

B

/

CD

N

G4

4

5

4]

4

1

[

D

A]

3

1

[

D

A6

4

7

4D

N

G]

0

1

[

D

A8

4

9

4]

8

0

[

D

AV

3

.

3

+0

5

1

5]

7

0

[

D

AD

V

S

R

-

C

M

P

)

1

(

2

5

3

5V

3

.

3

+D

V

S

R

-

C

M

P

)

1

(

4

5

5

5D

V

S

R

-

C

M

P

)

1

(

D

N

G6

5

7

5D

V

S

R

-

C

M

P

)

1

(

D

V

S

R

-

C

M

P

)

1

(

8

5

9

5D

N

GD

V

S

R

-

C

M

P

)

1

(

0

6

1

6#

4

6

K

C

A

)

1

(

V

3

.

3

+2

6

3

6D

N

GD

V

S

R

-

C

M

P

)

1

(

4

6

4095 tbl 05