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IDT7M9514S150M Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT7M9514S150M Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 7 page 2 1999 Integrated Device Technology, Inc. © IDT IDT7M9510 / IDT7M9514 SYSTEM FPGA The system FPGA is responsible for the following functions: Processor initialization, Reset Control, Device Decoding, Interrupt Masking / Mapping. PROCESSOR INITIALIZATION The 79RV4640 / 79RC64V474 requires a serial data stream for initializa- tion. The initialization process is handled by the system FPGA. RESET CONTROL Once the FPGA is loaded, the CPU is booted by sequencing the VCCOK, WARMRESET,COLDRESETlines. Atboot-up,theCPUappliesMODECLOCK to the FPGA to read out several bytes of configuration information using the MODEIN line. Thereisapushbuttonforresettingthe7M9510/7M9514. Thisisconnected to the FPGA through the SYSRESET signal. Additionally, a 2-pin header is provided for connection to an external reset switch. INTERRUPT STRUCTURE The system FPGA implements a basic interrupt controller that maps the variousinterruptsourcestotheCPUinterrupts. ItalsogivestheCPUtheability to mask interrupts and generate PCI interrupts. PCI INTERFACE TheGT-64011includesafullfeaturedhosttoPCIbridgewhichcanoperate as either a target or initiator. For improved performance the bridge contains 96 bytes of posted write and read prefetch buffers. TheGT-64011initiatesPCIcycleswheneithertheCPUortheDMAengine generates a bus cycle to PCI address space. These cycles can be either Memory, Interrupt Acknowledge, Special, I/O, or Configuration cycles. Con- figuration registers can be accessed from either the host bus or the PCI bus. The GT-64011 includes a full featured DRAM controller and generates all control signals for the DRAM SIMM. Further information can be found in the GT-64011 Data Sheet, available from Galileo Technology. PC16552DUALSERIALPORTCONTROLLER The PC16552D is a Dual Universal Asynchronous Receiver/Transmitter. EachindependentchannelissoftwarecompatiblewiththePC16550D. Further informationcanbefoundinthePC16552DDataSheet,availablefromNational Semiconductor. WATCHDOG TIMER The WatchDog Timer generates a non-maskable interrupt from a MAX706TCSA. It is used to control the system reset logic and to provide a watchdog reset. Further information can be found in the MAX706 Data Sheet, available from Maxim. BOARD OVERVIEW The IDT7M9510/9514 consists of the following functional blocks: IDT79RV4640/IDT79RC64V474 MIPS processor, Galileo GT-64011 PCI System Controller, DRAM memory, system Glue Logic (FPGA based), Flash/ EPROM and dual serial channels. The IDT7M9510/9514 CPU subsystem is designedtointerfacewithitstargetedsystemthroughastandardPCIMezzanine Card form factor. IDT79RV4640PROCESSOR The IDT79RV4640 is a high performance cost-effective MIPS processor targeted at embedded applications which runs at internal frequencies from 100MHz to 200MHz. Further information can be found in the 79RV4640 Data Sheet, available from IDT. IDT79RC64V474PROCESSOR TheIDT79RC64V474isahighperformancecost-effectiveMIPSprocessor targeted at embedded applications which runs at internal frequencies from 180MHzto250MHz. Furtherinformationcanbefoundinthe79RC64V474Data Sheet, available from IDT. GT-64011 PCI SYSTEM CONTROLLER The GT-64011 is a system support device from Galileo Technology, Inc. Thischipprovidesthebulkofthesystemcontrolandsupportfunctionsrequired foraMIPSRV4640/RC64V474CPUbasedsystem.TheGT-64011hasathree bus architecture. These three busses are: a CPU bus interface, a PCI bus interfaceandamemory/devicebusinterface.InadditiontheGT-64011contains a DRAM controller and a DMA controller. Further information can be found in the GT-64011 Data Sheet, available from Galileo Technology. DRAM The main memory is implemented using one standard 72-position DRAM SIMM providing a 32-bit path to memory. The main memory is designed to support one or two banks of DRAM which is dependent on the type of SIMM being used. One bank is supported when a single bank DRAM SIMM is used (e.g., 1M x 32), and two banks are supported when a double bank DRAM SIMM is used (e.g., 2M x 32). The design can use any standard DRAM SIMM containing 4MB (1M x 32), 8MB (2M x 32), 16 MB (4M x 32), or 32MB (8M x 32), 64MB (16M x 32), or 128MB (32M x 32) allowing the 7M9510/7M9514 to have up to a maximum of 128MB of memory. 60ns memory is recommended. The memory configuration is flexible and is field upgradeable. BOOT EPROM The Boot EPROM is a standard 512K x 8 EPROM which holds the boot code, the debug monitor and power-on diagnostics. (Socket supports Flash chip for development) FLASH MEMORY The 7M9510 / 7M9514 has 2MB of Flash on board, configured as 512K x 32. |
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