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CY7C1427BV18-200BZXI Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1427BV18-200BZXI
Description  36-Mbit DDR-II SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1427BV18-200BZXI Datasheet(HTML) 9 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1416BV18
CY7C1427BV18
CY7C1418BV18
CY7C1420BV18
Document Number: 001-07033 Rev. *B
Page 9 of 28
Application Example[1]
Truth Table for DDR-II [2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on
consecutive K and K rising edges.
L-H
L
L
D(A) at K(t + 1)
D(A + 1) at K(t + 1)
Read Cycle:
Load address; wait one and a half cycle; read data on
consecutive C and C rising edges.
L-H
L
H
Q(A) at C(t + 1)
Q(A + 1) at C(t + 2)
NOP: No Operation
L-H
H
X
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State
Previous State
Burst Address Table (CY7C1427BV18, CY7C1418BV18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. On CY7C1418BV18 and CY7C1420BV18, “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the
addresses sequence in the burst. On CY7C1416BV18 and CY7C1427BV18 “A” represents A + ‘0’ and A2 represents A + ‘1’.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
LD#
Vterm = 0.75V
Vterm = 0.75V
CC#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
K
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50ohms
R = 250ohms
R = 250ohms
[+] Feedback
[+] Feedback


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