Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1424BV18-300BZC Datasheet(PDF) 7 Page - Cypress Semiconductor

Part # CY7C1424BV18-300BZC
Description  36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1424BV18-300BZC Datasheet(HTML) 7 Page - Cypress Semiconductor

Back Button CY7C1424BV18-300BZC Datasheet HTML 3Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 4Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 5Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 6Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 7Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 8Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 9Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 10Page - Cypress Semiconductor CY7C1424BV18-300BZC Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 28 page
background image
PRELIMINARY
CY7C1422BV18
CY7C1429BV18
CY7C1423BV18
CY7C1424BV18
Document Number: 001-07035 Rev. *B
Page 7 of 28
Functional Overview
The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18,
CY7C1424BV18 are synchronous pipelined Burst SRAMs
equipped with a DDR-II Separate I/O interface which operates
with a read latency of one and half cycles when DOFF pin is
tied HIGH. When DOFF pin is set LOW or connected to VSS
the device will behave in DDR-I mode with a read latency of
one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing
is referenced to the rising edge of the output clocks, C/C (or
K/K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the rising edge of input clocks (K and
K). All synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks, C/C
(or K/K when in single clock mode). All synchronous control
(R/W, LD, BWS[x:0]) inputs pass through input registers
controlled by the rising edge of the input clock (K).
CY7C1423BV18 is described in the following sections. The
same
basic
descriptions
apply
to
CY7C1422BV18,
CY7C1429BV18, and CY7C1424BV18.
Read Operations
The CY7C1423BV18 is organized internally as two arrays of
1M x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to the Address inputs is
stored in the Read address register. Following the next K clock
rise the corresponding lowest-order 18-bit word of data is
driven onto the Q[17:0] using C as the output timing reference.
On the subsequent rising edge of C the next 18-bit data word
is driven onto the Q[17:0]. The requested data will be valid
0.45 ns from the rising edge of the output clock (C or C, or K
or K when in single clock mode, for 250-MHz and 200-MHz
devices). Read accesses can be initiated on every K clock
rise. Doing so will pipeline the data flow such that data is trans-
ferred out of the device on every rising edge of the output
clocks, C/C (or K/K when in single clock mode).
When Read access is deselected, the CY7C1423BV18 will
first complete the pending Read transactions. Synchronous
CQ
Echo Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
Input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to
GND or left unconnected.
DOFF
Input
DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
For normal operation, this pin can be connected to a pull-up through a 10-Kohm or less pull-up
resistor. The device will behave in DDR-I mode when the DLL is turned off. In this mode, the
device can be operated at a frequency of up to 167 MHz with DDR-I timing.
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
N/A
Not connected to the die. Can be tied to any voltage level.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as AC measurement points.
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply
Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
[+] Feedback
[+] Feedback


Similar Part No. - CY7C1424BV18-300BZC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1424BV18-300BZC CYPRESS-CY7C1424BV18-300BZC Datasheet
658Kb / 30P
   36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
More results

Similar Description - CY7C1424BV18-300BZC

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1422JV18 CYPRESS-CY7C1422JV18 Datasheet
678Kb / 28P
   36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422AV18 CYPRESS-CY7C1422AV18 Datasheet
466Kb / 28P
   36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422BV18 CYPRESS-CY7C1422BV18_07 Datasheet
658Kb / 30P
   36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422KV18 CYPRESS-CY7C1422KV18 Datasheet
944Kb / 32P
   36-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18 CYPRESS-CY7C1522AV18_07 Datasheet
686Kb / 30P
   72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522V18 CYPRESS-CY7C1522V18 Datasheet
446Kb / 28P
   72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392JV18 CYPRESS-CY7C1392JV18 Datasheet
1Mb / 26P
   18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392BV18 CYPRESS-CY7C1392BV18 Datasheet
483Kb / 27P
   18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522AV18 CYPRESS-CY7C1522AV18 Datasheet
1Mb / 28P
   72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392CV18 CYPRESS-CY7C1392CV18 Datasheet
695Kb / 30P
   18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com