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August 31, 2004

IDT 79RC32334—Rev. Y

Mode Bit Settings to Configure Controller on Reset

The following table lists the mode bit settings to configure the controller on cold reset.

Debug Signals

debug_cpu_dma_n

I/O

Z

Low

Debug CPU versus DMA Negated

De-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac-

tion was generated from the CPU.

Assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction

was generated from DMA.

Alternate function: modebit[6].

debug_cpu_ack_n

I/O

Z

Low

Debug CPU Acknowledge Negated

Indicates either a data acknowledge to the CPU or DMA.

Alternate function: modebit[4].

debug_cpu_ads_n

I/O

Z

Low

Debug CPU Address/Data Strobe Negated

Assertion indicates that either a CPU or a DMA transaction is beginning and that the mem_data[31:4] bus

has the current block address.

Alternate function: modebit[5].

debug_cpu_i_d_n

I/O

Z

Low

Debug CPU Instruction versus Data Negated

Assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a

CPU or DMA data transaction.

De-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a

CPU instruction transaction.

Alternate function: modebit[3].

Pin

Mode Bit

Description

Value

Mode Setting

ejtag_pcst[2:0]

2:0 MSB (2)

Clock Multiplier

MasterClock is multiplied internally to gener-

ate PClock

0

Multiply by 2

1

Multiply by 3

2

Multiply by 4

3

Reserved

4

Reserved

5

Reserved

6

Reserved

7

Reserved

debug_cpu_i_d_n

3

EndBit

0

Little-endian ordering

1

Big-endian ordering

debug_cpu_ack_n

4

Reserved

0

debug_cpu_ads_n

5

Reserved

0

debug_cpu_dma_n

6

TmrIntEn

Enables/Disables the timer interrupt on Int*[5]

0

Enables timer interrupt

1

Disables timer interrupt

mem_addr[17]

7

Reserved for future use

1

Table 2 Boot-Mode Configuration Settings (Part 1 of 2)

Name

Type

Reset

State

Status

Drive

Strength

Capability

Description

Table 1 Pin Description (Part 7 of 7)