6.42

2

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)

18 Mb DDR II SRAM Burst of 4

Commercial Temperature Range

output at the designated time in correspondence with the C and

C clocks.

Write operations are initiated by holding the Read/Write control

input (R/

W) low, the load control input (LD) low and presenting the write

address to the address port during the rising edge of K, which will latch

the address. On the following rising edge of K, the first word of the four

word burst must be present on the data input bus DQ[x:O], along with the

appropriate byte write or nibble write (

BWx or NWx) inputs. On the

following rising edge of

K, the second word of the data write burst will be

accepted at the device input with the designated (

BWx or NWx) inputs.

The subsequent K and

K rising edges will receive the last two words of

the four word burst, with their

BWx/NWx enables.

DDRII devices internally store four words of the burst as a single,

wide word and will retain their order in the burst. The x8 and x9 devices

do not have the ability to address to the single word level or change the

burst order; however the byte and nibble write signals can be used to

prevent writing any byte or individual nibbles, or combined to prevent

writing one word of the burst. The x18 and x36 DDRll devices have the

address bits, but the burst will continue in a linear sequence and wraps

around without incrementing the SA bits. When reading or writing x18

and x36 DDRll devices, the burst will begin at the designated address,

but if the burst is started at any other position than the first word of the

burst, the burst will wrap back on itself and read the first locations before

completing. The x18 and x36 DDRII devices can also use the byte write

signals to prevent writing any individual byte or word of the burst.

Output Enables

The DDRII SRAM automatically enables and disables the DQ[X:0]

outputs. When a valid read is in progress, and data is present at the

output, the output will be enabled. If no valid data is present at the output

(read not active), the output will be disabled (high impedance). The

echo clocks will remain valid at all times and cannot be disabled or turned

off. During power-up the DQ outputs will come up in a high impedance

state.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and Vss to allow the SRAM to adjust its output drive

impedance. The value of RQ must be 5X the value of the intended drive

impedance of the SRAM. The allowable range of RQ to guarantee

impedance matching with a tolerance of +/- 10% is between 175 ohms

every 1024 clock cycles to correct for drifts in supply voltage and tem-

perature. If the user wishes to drive the output impedance of the SRAM

The C and

C clocks may be used to clock the data out of the

output register during read operations and to generate the echo clocks.

C and

C must be presented to the SRAM within the timing tolerances.

The output data from the DDRII will be closely aligned to the C and

C

input, through the use of an internal DLL. When C is presented to the

DDRII SRAM, the DLL will have already internally clocked the data to

arrive at the device output simultaneously with the arrival of the

C clock.

The C and second data item of the burst will also correspond. The third

and fourth data words will follow on the next clock cycle of the

C and C,

respectively.

Single Clock Mode

The DDRII SRAM may be operated with a single clock pair. C

and

C may be disabled by tying both signals high, forcing the outputs

and echo clocks to be controlled instead by the K and

K clocks.

DLL Operation

The DLL in the output structure of the DDRII SRAM can be used

to closely align the incoming clocks C and

C with the output of the data,

generating very tight tolerances between the two. The user may disable

the DLL by holding

Doff low. With the DLL off, the C and C (or K and K

if C and

C are not used) will directly clock the output register of the

SRAM. With the DLL off, there will be a propagation delay from the time

the clock enters the device until the data appears at the output.

Echo Clock

The echo clocks, CQ and

CQ, are generated by the C and C

clocks (or K,

K if C, C are disabled). The rising edge of C generates the

rising edge of CQ, and the falling edge of

CQ. The rising edge of C

generates the rising edge of

CQ and the falling edge of CQ. This

scheme improves the correlation of the rising and falling edges of the

echo clock and will improve the duty cycle of the individual signals.

The echo clock is very closely aligned with the data, guarantee-

ing that the echo clock will remain closely correlated with the data, within

the tolerances designated.

Read and Write Operations

Read operations are initiated by holding Read/Write control input

(R/

W) high, the load control input (LD) low and presenting the read

address to the address port during the rising edge of K, which will latch

the address. The data will then be read and will appear at the device

Clocking

The DDRII SRAM has two sets of input clocks, namely the K,

K

clocks and the C,

C clocks. In addition, the QDRII has an output “echo”

clock, CQ,

CQ.

The K and

K clocks are the primary device input clocks. The K

clock is used to clock in the control signals (

LD, R/W and BWx or NWx),

the address, and the first and third words of the data burst during a write

operation. The

K clock is used to clock in the control signals (BWx or

NWx), and the second and fourth words of the data burst during a write

operation. The K and

K clocks are also used internally by the SRAM. In

the event that the user disables the C and

C clocks, the K and K clocks

will also be used to clock the data out of the output register and generate

the echo clocks.