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75N42102 Datasheet(PDF) 2 Page - Integrated Device Technology |
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75N42102 Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 3 page  2 Network Search Engine 32K x 72 Entries Datasheet Brief 75N42102 SRAM Interface The NSE provides all required address and control signals for a glueless SRAM interface. The NSE provides a pipelined bypass path for reads or writes to the external SRAM. The ASIC/FPGA handles the pipelining of the data to and from the SRAM. Registers There are four basic types of registers supported: ■ ConfigurationRegistersareusedatinitializationtodefinethe segmentation of the entries, timing of outputs and the SRAM interface. ■ Global Mask Registers are provided to support Lookup instructions by masking individual bits during a search. ■ Search Result Registers are used to store the resulting index of a search from a Lookup operation. ■ Reply Width Registers are used with Lookup operations. Functional Highlights Figure 1.1 Bus Interface The NSE utilizes a dual bus interface consisting of the NSE Request Bus and the NSE Response Bus. The NSE Request Bus is comprised of the Command Bus and the RequestDataBus. TheCommandBushandlestheinstructiontotheNSE while the Request Data Bus is the main data path to the NSE. The72bitbi-directionalRequestDataBusfunctionsasamultiplexed address and data bus, which performs the writing and reading of NSE entries, as well as presenting lookup data to the device. The NSE Response Bus is comprised of an independent unidirec- tional Index Bus which drives the result of the lookup (or index) to either an SRAM device or an ASIC. In addition to driving the Index, the NSE ResponseBusalsodrivestheassociatedSRAMcontrolsignals( CE/OE, and WE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices. Data and Mask Array The NSE has Data cell entries and associ- atedMaskcellentriesasshowninFig.1.1. This combination of Data and Mask cell entries en- ables the NSE to store 0, 1 or X, making it a full ternary Network Search Engine. During a lookup operation, both arrays are used along with a Global Mask Register to find a match to a requested data word. A6457 drw 03 Da t a Mask Features ■ ■ ■ ■ ■ Full Ternary 32K x 72 bit content addressable memory ■ ■ ■ ■ ■ GlobalMaskRegisters ■ ■ ■ ■ ■ 40/72/144/288multiplewidthlookups ■ ■ ■ ■ ■ 200M sustained lookups per second at 72 and 144 width lookups ■ ■ ■ ■ ■ Dualbusinterface ■ ■ ■ ■ ■ Cascadable to 8 devices with no glue logic or latency penalty ■ ■ ■ ■ ■ GluelessinterfacetostandardZBT™or Synchronous Pipelined Burst SRAMs ■ ■ ■ ■ ■ BoundaryScanJTAGInterface(IEEE1149.1compliant) ■ ■ ■ ■ ■ 1.5V match power supply ■ ■ ■ ■ ■ 2.5V core and I/O power supply Command Bus TheCommandBusloadsthe specificinstructionsintotheNSE.These include: ■ Read or Write A Read or Write instruction operates on a specified data entry, mask entry, register or external SRAM. ■ SRAM No Wait Read AnSRAMNoWaitReadisaReadinstructiontoanexternalSRAMthat canbepipelinedwithinaseriesofoperationsanddoesnotrequiretheuser to wait for the Read to complete before loading the next instruction. ■ Lookup A lookup can be requested in 40-bit, 72-bit, 144-bit or 288-bit widths. ■ SMDL Lookup ThethreeSMDLLookupinstructionsoffertheabilitytosimultaneously search in mutually exclusive databases which increases the search rate up to 200 MSPS. |
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