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CY7C1411AV18
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
Document Number: 38-05614 Rev. *C
Page 2 of 28
Logic Block Diagram (CY7C1411AV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
20
8
32
8
NWS[1:0]
VREF
Write
Reg
16
A(19:0)
20
C
C
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
Logic Block Diagram (CY7C1426AV18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
9
36
9
BWS[0]
VREF
Write
Reg
18
A(19:0)
20
C
C
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
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