CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Document Number: 38-05548 Rev. *E
Page 6 of 30
Pin Definitions
Name
IO
Description
A0, A1, A
Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]
are sampled active. A1: A0 are fed to the two-bit counter..
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (all bytes are written, regardless of the values
on BWX and BWE).
BWE
Input-
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
CLK
Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 [2] to select or deselect the device. ADSP is ignored
if CE1 is HIGH. CE1 is sampled only when a new external address is loaded.
CE2 [2]
Input-
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 [2] to select or deselect the device. CE2 is sampled
only when a new external address is loaded.
CE3 [2]
Input-
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select or deselect the device. Not connected for
BGA. Where referenced, CE3 [2] is assumed active throughout this document for
BGA. CE3 is sampled only when a new external address is loaded.
OE
Input-
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the
IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ
pins are tri-stated, and act as input data pins. OE is masked during the first clock
of a read cycle when emerging from a deselected state.
ADV
Input-
Synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
ADSC
Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ sleep input, active HIGH. When asserted HIGH places the device in a
non-time-critical sleep condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull down.
DQs, DQPs
IO-
Synchronous
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are
placed in a tri-state condition.
VDD
Power Supply
Power supply inputs to the core of the device.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
