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CY7C1382F-200BGXC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1382F-200BGXC
Description  18-Mbit (512K x 36/1M x 18) Pipelined SRAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1382F-200BGXC Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C1380D, CY7C1380F
CY7C1382D, CY7C1382F
Document #: 38-05543 Rev. *E
Page 8 of 30
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW, BWE, and BWX) and
ADV inputs are ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides byte write capability that is described in the write
cycle descriptions table. Asserting the byte write enable input
(BWE) with the selected byte write (BWX) input, will selectively
write to only the desired bytes. Bytes not selected during a
byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common IO device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BWX) are asserted active to conduct a write to the
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common IO device, the output enable (OE) must be deserted
HIGH before presenting data to the DQs inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The
CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides a two-bit wraparound counter, fed by A1: A0, that
implements an interleaved or a linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns


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