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CY7C1399BN Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY7C1399BN
Description  256K (32K x 8) Static RAM
Download  8 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1399BN Datasheet(HTML) 3 Page - Cypress Semiconductor

  CY7C1399BN Datasheet HTML 1Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 2Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 3Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 4Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 5Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 6Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 7Page - Cypress Semiconductor CY7C1399BN Datasheet HTML 8Page - Cypress Semiconductor  
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CY7C1399BN
Document #: 001-06490 Rev. *A
Page 3 of 8
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
CIN: Addresses
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = 3.3V
5
pF
CIN: Controls
6
pF
COUT
Output Capacitance
6
pF
AC Test Loads and Waveforms[5]
Switching Characteristics Over the Operating Range[5]
Parameter
Description
-12
-15
-20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
12
15
20
ns
tAA
Address to Data Valid
12
15
20
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE
CE LOW to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
5
6
7
ns
tLZOE
OE LOW to Low Z[6]
0
0
0
ns
tHZOE
OE HIGH to High Z[6, 7]
5
6
6
ns
tLZCE
CE LOW to Low Z[6]
3
3
3
ns
tHZCE
CE HIGH to High Z[6, 7]
6
7
7
ns
tPU
CE LOW to Power-Up
0
0
0
ns
tPD
CE HIGH to Power-Down
12
15
20
ns
Write Cycle[8, 9]
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE LOW to Write End
8
10
12
ns
tAW
Address Set-Up to Write End
8
10
12
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
8
10
12
ns
tSD
Data Set-Up to Write End
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z[8]
7
7
7
ns
tLZWE
WE HIGH to Low Z[6]
3
3
3
ns
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and capacitance CL = 30 pF.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, tHZWE are specified with CL = 5 pF as in AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
3.0V
3.3V
OUTPUT
R1 317
R2
351
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
OUTPUT
1.73V
Equivalent to:
THÉVENINEQUIVALENT
ALL INPUT PULSES
167
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