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CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 2 of 27
Logic Block Diagram (CY7C1392BV18)
1M x 8
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
LD
Q[7:0]
Control
Logic
Reg.
Reg.
Reg.
8
8
16
Write
8
NWS0
VREF
Data Reg
Write
Data Reg
Memory
Array
1M x 8
Memory
Array
8
8
20
8
C
C
NWS1
R/W
LD
R/W
CQ
CQ
DOFF
Logic Block Diagram (CY7C1992BV18)
1M x 9
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
LD
Q[8:0]
Control
Logic
Reg.
Reg.
Reg.
9
9
18
Write
9
BWS0
VREF
Data Reg
Write
Data Reg
Memory
Array
1M x 9
Memory
Array
9
9
20
9
C
C
R/W
LD
R/W
CQ
CQ
DOFF
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