6.42

3

IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)

18 Mb DDR II SIO SRAM Burst of 2

Commercial and Industrial Temperature Ranges

Symbol

Pin Function

Description

D[X:0]

Input

Synchronous

Data input signals, sampled on the rising edge of K and

K clocks during valid write operations

2M x 8 -- D[7:0]

2M x 9 -- D[8:0]

1M x 18 -- D[17:0]

512K x 36 -- D[35:0]

Input

Synchronous

Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising

edge of

K clocks during write operations. Used to select which byte is written into the device during the current

portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on the same

edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and

not written in to the device.

2M x 9 --

1M x 18 --

512K x 36 --

NW0 NW1

Input

Synchronous

Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.

Sampled on the rising edge of the K and

K clocks during write operations. Used to select which nibble is written

into the device during the current portion of the write operations. Nibbles not written remain unaltered. All the

nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the

corresponding nibble of data to be ignored and not written in to the device.

2M x 8--

NW0 controls D[3:0] and NW1 controls D[7:4]

SA

Input

Synchronous

Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.

Q[X:0]

Output

Synchronous

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on

the rising edge of both the C and

C clocks during Read operations or K and K when operating in single clock

mode. When the Read port is deselect ed, Q[X:0] are automatically three-stated.

LD

Input

Synchronous

Load Control Logic. Sampled on the rising edge of K. If

LD is low, a two word burst read or write operation will

be initiated as designated by the R/

W input. If LD is high during the rising edge of K, operations in progress will

complete, but new operations will not be initiated.

R/

W

Input

Synchronous

Read or Write Control Logic. If

LD is low during the rising edge of K, the R/W indicates whether a new operation

should be a read or write. If R/

W is high, a read operation will be initiated, if R/W is low, a write operation will be

initiated. If the

LD input is high during the rising edge of K, the R/W input will be ignored.

CInput Clock

Positive Output Clock Input. C is used in conjunction with

C to clock out the Read data from the device. C and

C can be used together to deskew the flight times of various devices on the board back to the controller. See

application example for further details.

C

Input Clock

Negative Output Clock Input.

C is used in conjunction with C to clock out the Read data from the device. C and

C can be used together to deskew the flight times of various devices on the board back to the controller. See

application example for further details.

KInput Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive

out data through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.

K

Input Clock

Negative Input Clock Input.

K is used to capture synchronous inputs being presented to the device and to drive

out data through Q[X:0] when in single clock mode.

CQ,

CQ

Output Clock

Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data

outputs and can be used as a data valid indication. These signals are free running and do not stop when the

output data is three stated.

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. Q[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and

This pin cannot be connected directly to GND or left unconnected.

6432 tbl 02a

Pin Definitions