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IDTIDT71P79604267BQ Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDTIDT71P79604267BQ Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 23 page 6.42 2 IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit) 18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges Clocking The DDRII SIO SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII SIO has an output “echo” clock, CQ, CQ. The K and K clocks are the primary device input clocks. The K clock is, used to clock in the control signals ( LD, R/W and BWx or NWx), the address, and the first word of the data burst during a write operation. The K clock is used to clock in the control signals (BWx or NWx) and the second word of the data burst during a write operation. The K and K clocks are also used internally by the SRAM. In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the SRAM within the timing tolerances. The output data from the DDRII SIO will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the DDRII SIO SRAM, the DLL will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the C clock. The C and second data item of the burst will also correspond. Single Clock Mode The DDRII SIO SRAM may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the DDRII SIO SRAM can be used to closely align the incoming clocks C and C with the output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding Doff low. With the DLL off, the C and C (or K and K if C and C are not used) will directly clock the output register of the SRAM. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. Echo Clock The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves All interfaces of the DDR II SIO are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if necessary. The device has a VDDQ and a separate Vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8V VDD. The output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. Read and Write Operations DDRII SIO devices internally store the two words of the burst as a single wide word and the words will retain their burst order. There is no ability to address an individual word level in a burst, as is possible in the DDRII common I/O devices. The byte and nibble write signals can be used to prevent writing to any individual bytes, or combined to prevent writing word(s) of the burst. Read operations are initiated by holding Read/Write control input (R/ W) high, the load control input (LD) low and presenting the read address to the address port during the rising edge of K, which will latch the address. The data will then be read and will appear at the device output at the designated time in correspondence with the C and C clocks. Write operations are initiated by holding the Read/Write control input (R/ W) low, the load control input (LD) low and presenting the write address to the address port during the rising edge of K, which will latch the address. On the following rising edge of K, the first word of the two word burst must be present on the data input bus DQ[x:O], along with the appropriate byte write or nibble write ( BWx or NWx) inputs. On the following rising edge of K, the second half of the data write burst will be accepted at the device input with the designated ( BWx or NWx) inputs. Output Enables The DDRII SIO SRAM automatically enables and disables the Q[X:0] outputs. When a valid read is in progress, and data is present at the output, the output will be enabled. If no valid data is present at the output (read not active), the output will be disabled (high impedance). The echo clocks will remain valid at all times and cannot be disabled or turned off. During power-up the Q outputs will come up in a high impedance state. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output drive imped- ance. The value of RQ must be 5X the value of the intended drive impedance of the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and tem- perature. If the user wishes to drive the output impedance of the SRAM to it’s lowest value, the ZQ pin may be tied to VDDQ. generated by the same source that drives the data output, the relation- ship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. |
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